DRAM controller including bus-width selection and data inversion

Details DRAM controller including bus-width selection and data inversion DRAM controller including bus-width selection and data inversion

1993-09-27

1997-05-13

Tung, Kee M.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

395510, 395518, 395524, 345185, 345189, 345201, G06F 1200

Patent

active

056301065

ABSTRACT:
A DRAM is constructed by a memory section, a multiplexer (MPX), an inverting circuit and a non-inverting circuit. The memory section stores data transferred through a data bus. The multiplexer selects a width of the data bus based on a mode signal for designating the bus width. The mode signal is shown by a MODE0 signal. The inverting circuit inverts writing data and/or reading data based on a mode signal for designating inversion of data. This mode signal is shown by a MODE1 signal. The non-inverting circuit stops transmission of non-inverted data at an inverting time and passes or transmits data at a non-inverting time on the basis of the MODE1 signal. In this structure, a plurality of access methods can be used with respect to a single DRAM so that extendability of the DRAM is improved and a high speed access operation is performed. Further, it is possible to cope with reverse logics of white data with respect to data of YMC (yellow, magenta, cyan) and RGB (red, green, blue) by a simplified circuit structure and a short processing time. A controller using this DRAM is also shown.

REFERENCES:
patent: 4766570 (1988-08-01), Yamaguchi et al.
patent: 5055661 (1991-10-01), Gochi
patent: 5283877 (1994-02-01), Gastinel
patent: 5307320 (1994-04-01), Farrer
patent: 5450342 (1995-09-01), Kimura

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