DRAM controller cache

Details DRAM controller cache DRAM controller cache

1988-06-24

1989-09-26

Popek, Joseph A.

Static information storage and retrieval

Addressing

Multiplexing

36523003, 3652385, G11C 700

Patent

active

048706221

ABSTRACT:
A method of minimizing memory access time on a memory with multiplexed address inputs between data stored in locations in memory in the same row but in different columns. First data is accessed at a predetermined column and row location. The predetermined row location of the first data is then recorded. The location of second data is then recorded. Then the locations of the first and second data are compared. A row compare signal is generated if the row value of both first and second data are identical. Only the column address is varied in response to the row compare signal.

REFERENCES:
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 4803621 (1989-02-01), Kelly

Affiliated with

Also associated with

Rating

DRAM controller cache does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM controller cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM controller cache will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-192729