Dram column address latching technique

Details Dram column address latching technique Dram column address latching technique

1991-04-05

1994-04-19

Sikes, William L.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

3652335, G11C 800

Patent

active

053052838

ABSTRACT:
Apparatus and a method for latching a column address in a DRAM, having increased speed and no race conditions. The method is comprised of the steps of receiving column select and column address input signals, enabling detection and indication, by generation of an indication signal, of the presence of each stable column address input signal upon the presence of a column select signal, summing the indication signals, and operating a latch by each of the column address input signals whereby a DRAM column can be addressed upon enabling by the summed indication signals, whereby the latching is not enabled without a first indication of the presence of a stable column address and whereby the first indication is prevented without the earlier presence of a column select signal.

REFERENCES:
patent: 4242738 (1980-12-01), Dingwall
patent: 4633442 (1986-12-01), Borghese
patent: 5036495 (1991-07-01), Busch et al.
patent: 5077690 (1991-12-01), Smith
patent: 5083296 (1992-01-01), Hara et al.
patent: 5148535 (1992-09-01), Ballard

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