DRAM cells having stacked capacitors of fin structures and metho

Details DRAM cells having stacked capacitors of fin structures and metho DRAM cells having stacked capacitors of fin structures and metho

1992-02-18

1994-03-01

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437919, H01L 2170

Patent

active

052907260

ABSTRACT:
A method of making dynamic random access memory cells having stacked capacitors of fin structures enabling the extension of the capacitor regions, irrespective of the used design rule. The method uses insulation layers having different etch selectivities, in order to extend the area of capacitor regions. The method comprises the steps of depositing three insulation layers on a semiconductor substrate, etching the uppermost insulation layer partially and then wet etching the intermediate insulation layer to remove its exposed portions completely and its hidden portions disposed beneath the third insulation layer partially to a predetermined length for extending the area of capacitors regions. The wet etch time of the insulation layers are controlled to control the etched length. With this extension of the area of capacitor regions, the buried contacts are formed by wet etching and are stable. Also, the number of mask processes is reduced, thereby enabling the manufacturing process to be simplified.

REFERENCES:
patent: 4614564 (1986-09-01), Sheldon et al.
patent: 4641166 (1987-02-01), Takemae et al.
patent: 4649406 (1987-03-01), Takemae et al.
patent: 4754313 (1988-06-01), Takemae et al.
patent: 4902377 (1990-02-01), Berglund et al.
patent: 4953126 (1990-08-01), Ema
patent: 4970564 (1990-11-01), Kimura et al.
patent: 4974040 (1990-11-01), Taguchi et al.
patent: 5014103 (1991-05-01), Ema
patent: 5021357 (1991-06-01), Taguchi et al.
A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-Line Structure by Kimura, Kawamoto, Kure, Hasegawa, Etoh, Aoki, Takeda, Sunami and Itoh-Central Research Laboratory, Hitachi Ltd. (IEDM 1988, pp. 596-599).
3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs by Ema, Kawanago, Nishi, Yoshida, Nishibe, Yabu, Kodama Nakano and Taguchi-Fujitsu Laboratories Limited (IEDM 1988, pp. 592-595).

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