Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-05-02
2004-09-28
Abraham, Fetsum (Department: 2826)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S438000, C438S381000, C438S689000
Reexamination Certificate
active
06797590
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a DRAM cell structure capable of high integration and a fabrication method thereof; and, more particularly, to a vertical cylindrical DRAM cell structure capable of high integration connected to a trench-type capacitor and a fabrication method thereof.
BACKGROUND OF THE INVENTION
A DRAM is a device formed by combination of many memory cells composed of a transistor and a capacitor. Recently, DRAMs are being integrated in higher density in response to demands for larger memory capacity. Therefore, techniques for reducing a memory cell size to integrate more memory cells in a confined space have been required.
FIG. 1
illustrates a conventional DRAM cell structure. As shown in
FIG. 1
, a conventional DRAM cell structure includes a transistor device formed horizontally on a silicon substrate, and a capacitor device having a plate electrode and a storage node electrode formed on a stacked layer over the transistor device.
However, the conventional horizontal DRAM cell structure shown in
FIG. 1
has drawbacks. First, integration density is limited due to word-line size and length. Second, it is difficult to secure a large enough size of the capacitor for sufficient capacitance.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a vertical cylindrical DRAM cell structure connected to a trench-type capacitor capable of high integration and a fabrication method thereof.
In accordance with one aspect of the present invention, there is provided a DRAM cell structure capable of high integration, including: a trench-type capacitor formed in a lower region of a trench, the trench being made vertically and cylindrically in a silicon substrate; a transistor formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor.
In accordance with another aspect of the present invention, there is provided a method for fabricating a DRAM cell structure capable of high integration, including the steps of (a) forming a trench vertically and cylindrically in a silicon substrate; (b) forming a trench-type capacitor having a cylindrical plate electrode and a storage node electrode on a lower region of the trench; (c) forming a vertical cylindrical transistor cell structure connected to the trench-type capacitor on an upper region of the trench.
REFERENCES:
patent: 5291438 (1994-03-01), Witek et al.
patent: 6496401 (2002-12-01), Weis
Abraham Fetsum
Dongbu Electronics Co. Ltd.
Jacobson & Holman PLLC
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