Dram cell in which a silicon-germanium alloy layer having a roug

Details Dram cell in which a silicon-germanium alloy layer having a roug Dram cell in which a silicon-germanium alloy layer having a roug

1991-07-10

1992-07-14

Griffin, Donald A.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

437 60, H01G 410, H01L 2170

Patent

active

051308851

ABSTRACT:
A dynamic random access memory cell in which a silicon-germanium alloy layer having a rough surface morphology is utilized for the capacitive surface of the storage-node plate of the cell capacitor. To create a DRAM array having such cells, a silicon-germanium alloy is deposited, typically via rapid thermal chemical vapor deposition, on top of a single crystalline silicon or polycrystalline silicon storage-node plate layer under conditions which favor three-dimensional growth in the form of macroscopic islanding (i.e., a high concentration of germanium in precursor gases and relatively high deposition temperature). A cell dielectric layer, which exhibits the property of bulk-limited conduction (e.g., silicon nitride), is utilized. Except for the deposition of the silicon-germanium alloy, array processing is conventional.

REFERENCES:
patent: 4882649 (1989-11-01), Chen et al.
patent: 4931897 (1990-06-01), Tsukamoto et al.
patent: 5036020 (1991-07-01), Tigelaar
"Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron Drams", T. Mine et al., 1989, pp. 137-140.
"Optimization Of Process Conditions For Selective Deposition Of Polycrystalline Si.sub.x Ge.sub.1-x Alloys In A Rapid Thermal Process", M. Sanganeria et al., Abstract No. 350.

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