DRAM cell having raised source, drain and isolation

Details DRAM cell having raised source, drain and isolation DRAM cell having raised source, drain and isolation

1993-12-17

1994-11-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 60, 437919, 257301, H01L 2700, H01L 2170

Patent

active

053690494

ABSTRACT:
A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

REFERENCES:
patent: 4688063 (1987-08-01), Lu et al.
patent: 4873205 (1989-10-01), Critchlow et al.
patent: 4983544 (1991-01-01), Lu et al.
patent: 5214603 (1993-05-01), Dhong et al.
patent: 5272102 (1993-12-01), Hun et al.

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