DRAM-cell having an isolation merged trench and its method of ma

Details DRAM-cell having an isolation merged trench and its method of ma DRAM-cell having an isolation merged trench and its method of ma

1990-09-04

1993-06-29

Fourson, George

Fishing, trapping, and vermin destroying

437 38, H01L 21265

Patent

active

052234479

ABSTRACT:
A method for manufacturing a DRAM cell is provided having an isolation merged trench for applying to 16 megabit and 64 megabit DRAM cells, which includes the steps forming a primary dielectric for a capacitor within the interior of a trench, depositing an n.sup.+ doped polysilicon, forming a secondary dielectric and then stacking polysilicon thereon and connecting the polysilicon within an n.sup.+ diffusion layer of the bottom of the trench for forming a plate. As a result of this method all of the capacitors disposed between the n.sup.+ polysilicon storing electrode and the n.sup.+ polysilicon plate as well as the polysilicon storing electrode and the n.sup.+ diffusion layer plate are utilized as a storing capacitor.

REFERENCES:
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patent: 4994409 (1991-02-01), Yoon et al.
patent: 5010379 (1991-04-01), Ishii
patent: 5041887 (1991-08-01), Kumagai et al.
patent: 5047815 (1991-09-01), Yashuira et al.
Kaga, T., et al, "Half Vcc Sheath-Plate . . . Buried Plate Wiring", Trans. on Electron Dev. 35(8), 8, 1988, pp. 1257-1263.

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