Dram cell having a stacked capacitor with a tantalum lower plate

Details Dram cell having a stacked capacitor with a tantalum lower plate Dram cell having a stacked capacitor with a tantalum lower plate

1991-11-15

1992-08-25

Griffin, Donald

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

357 236, 357 51, 437 52, H01G 406, H01L 2170, H01L 2968

Patent

active

051424380

ABSTRACT:
An improved DRAM cell having a tantalum metal lower plate, a tantalum-silicide buried contact, and a tantalum oxide capacitor dielectric layer is disclosed. Also disclosed are several methods for fabricating the improved cell. Fabrication of an array of the improved cells proceeds through the storage-node contact opening stage in a manner consistent with the fabrication process utilized for conventional stacked-cell DRAM arrays. The process for fabricating the improved cells deviates from convention after storage-node contact openings are formed. A tantalum metal layer is conformally deposited over the wafer surface, patterned and etched to create individual storage-node plates. The wafer is then subjected to an elevated temperature step in an oxygen ambient, which creates both a tantalum silicide layer at the tantalum-silicon interface of each storage-node contact, and a tantalum oxide dielectric layer on the exposed surfaces of each storage-node plate. The tantalum oxide layer then annealed in order to reduce its leakage current characteristics. Following the annealing step, a thin barrier layer of a material such as silicon nitride is blanket deposited. This is followed by the deposition of a polysilicon cell plate layer.

REFERENCES:
patent: 4432035 (1984-02-01), Hsieh et al.
patent: 4971655 (1990-11-01), Stefano et al.
patent: 5012310 (1991-04-01), Kimura et al.
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5079670 (1992-01-01), Tigelaar et al.

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