Dram cell and array to store two-bit data having merged stack ca

Details Dram cell and array to store two-bit data having merged stack ca Dram cell and array to store two-bit data having merged stack ca

1998-02-04

1999-07-06

Chaudhuri, Olik

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

438396, 257306, H01L 218242

Patent

active

059207850

ABSTRACT:
A twin bit DRAM cell capable of storing two bits of digital data as stored charge within the DRAM cell is disclosed. The twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The pass transistors each have a source connected to a bit line voltage generator to control placement of the charge within the twin bit DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain of the first pass transistor and a bottom plate connected to a first biasing voltage source. The stack capacitor has a first plate connected to the drain of the second pass transistor and a second plate connected to a second biasing voltage generator. Twin bit DRAM cells will be arranged in a plurality of rows and columns to form an array of twin bit DRAM cells.

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