dRAM cell and array

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Details

357 234, 357 2312, 357 51, 357 55, H01L 2978, H01L 2702, H01L 2906

Patent

active

048901458

ABSTRACT:
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. The transistor gate fills the upper portion of the trench, and a heavily doped other plate of the capacitor fills the lower portion of the trench and makes contact with the substrate through the bottom of the trench.

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