Dram capacitor structure

Details Dram capacitor structure Dram capacitor structure

1994-05-06

1995-01-10

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 52, 437 60, 437919, H01L 2170

Patent

active

053806735

ABSTRACT:
A new structure and method for fabricating a stacked capacitor with increased capacitance and which is more manufacturable was accomplished. The stacked capacitor is part of a dynamic random access memory (DRAM) cell for storing charge on the capacitor and together with a field effect transistor (MOSFET) make up the individual DRAM storage cells on a DRAM chip. Fabricating this improved stacked capacitor involves using an additional electrically conducting layer in the polysilicon layer of the bottom electrode. For example, this layer can be composed from materials in the metal nitride group having high conductivity. One preferred choice being titanium nitride (TiN). The bottom electrode is formed by depositing and patterning a thin layer of polysilicon and a thin layer of the electrically conducting layer and then depositing an upper layer of polysilicon from which vertical sidewalls are formed. The conducting layer provides an etch end point for accurately etching to the correct depth. This provided for a repeatable and more manufacturable process. The stacked capacitor is then completed by depositing a high dielectric constant insulator layer over the bottom electrode and forming a top capacitor electrode to complete the stacked capacitor. The bottom electrode contacts one source/drain contacts of the MOSFET and the bit line contacts the other source/drain contact completing the improved DRAM cell.

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"A Newly Designed Planar Stacked Capacitor Cell with High dielectric Constant Film for 256mbit DRAM", by T. Eimori et al., IEEE International Electronic Device Meeting Proceedings, Dec. 1993, pp. 631-634.

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