Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
2005-12-27
2005-12-27
Riley, Shawn (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
C365S226000, C365S189090, C327S111000
Reexamination Certificate
active
06980448
ABSTRACT:
A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtnthrough the transistors. The boosting capacitors are charge by Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.
REFERENCES:
patent: 3761899 (1973-09-01), McKenny et al.
patent: 3790812 (1974-02-01), Fry
patent: 3801831 (1974-04-01), Dame
patent: 3942047 (1976-03-01), Buchanan
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4000412 (1976-12-01), Rosenthal et al.
patent: 4001606 (1977-01-01), Dingwall
patent: 4037114 (1977-07-01), Stewart et al.
patent: 4039862 (1977-08-01), Dingwall et al.
patent: 4047091 (1977-09-01), Hutchines et al.
patent: 4080539 (1978-03-01), Stewart
patent: 4106086 (1978-08-01), Holbrook et al.
patent: 4189782 (1980-02-01), Dingwall
patent: 4199806 (1980-04-01), Patterson, III
patent: 4208595 (1980-06-01), Gladstein
patent: 4216390 (1980-08-01), Stewart
patent: 4271461 (1981-06-01), Hoffmann et al.
patent: 4279010 (1981-07-01), Morihisa
patent: 4307333 (1981-12-01), Hargrove
patent: 4344003 (1982-08-01), Harmon et al.
patent: 4344005 (1982-08-01), Stewart
patent: 4403158 (1983-09-01), Slemmer
patent: 4433253 (1984-02-01), Zapisek
patent: 4442481 (1984-04-01), Brahmbhatt
patent: 4471290 (1984-09-01), Yamaguchi
patent: 4486670 (1984-12-01), Chan et al.
patent: 4533843 (1985-08-01), McAlexander, III et al.
patent: 4543500 (1985-09-01), McAlexander et al.
patent: 4581546 (1986-04-01), Allan
patent: 4583157 (1986-04-01), Kirsch et al.
patent: 4616303 (1986-10-01), Mauthe
patent: 4621315 (1986-11-01), Vaughn et al.
patent: 4628214 (1986-12-01), Leuschner
patent: 4639622 (1987-01-01), Goodwin et al.
patent: 4642798 (1987-02-01), Rao
patent: 4656373 (1987-04-01), Plus
patent: 4670861 (1987-06-01), Shu et al.
patent: 4678941 (1987-07-01), Chao et al.
patent: 4679134 (1987-07-01), Bingham et al.
patent: 4689504 (1987-08-01), Raghunathan et al.
patent: 4692638 (1987-09-01), Stiegler
patent: 4697252 (1987-09-01), Furuyama
patent: 4716313 (1987-12-01), Hori et al.
patent: 4730132 (1988-03-01), Watanabe et al.
patent: 4733108 (1988-03-01), Truong
patent: 4740918 (1988-04-01), Okajima
patent: 4751679 (1988-06-01), Dehganpour
patent: 4798977 (1989-01-01), Sakui et al.
patent: 4807104 (1989-02-01), Floyd et al.
patent: 4807190 (1989-02-01), Ishii et al.
patent: 4811304 (1989-03-01), Matsuda et al.
patent: 4814647 (1989-03-01), Tran
patent: 4820941 (1989-04-01), Dolby et al.
patent: 4823318 (1989-04-01), D'Arrigo et al.
patent: 4837462 (1989-06-01), Watanabe et al.
patent: 4843256 (1989-06-01), Scade et al.
patent: 4857763 (1989-08-01), Sakurai et al.
patent: 4873673 (1989-10-01), Hori et al.
patent: 4878201 (1989-10-01), Nakaizumi
patent: 4881201 (1989-11-01), Sato
patent: 4888738 (1989-12-01), Wong et al.
patent: 4906056 (1990-03-01), Taniguchi
patent: 4920280 (1990-04-01), Cho et al.
patent: 4951259 (1990-08-01), Sato et al.
patent: 4961007 (1990-10-01), Kumanoya et al.
patent: 4982317 (1991-01-01), Mauthe
patent: 5010259 (1991-04-01), Inoue et al.
patent: 5018107 (1991-05-01), Yoshida
patent: 5023465 (1991-06-01), Douglas et al.
patent: 5031149 (1991-07-01), Matsumoto et al.
patent: 5038325 (1991-08-01), Douglas et al.
patent: 5038327 (1991-08-01), Akaogi
patent: 5051959 (1991-09-01), Nakano et al.
patent: 5059815 (1991-10-01), Bill et al.
patent: 5086238 (1992-02-01), Watanabe et al.
patent: 5101381 (1992-03-01), Kouzi
patent: 5103113 (1992-04-01), Inui et al.
patent: 5150325 (1992-09-01), Yanagisawa et al.
patent: 5151616 (1992-09-01), Komuro
patent: 5159215 (1992-10-01), Murotani
patent: 5196996 (1993-03-01), Oh
patent: 5197033 (1993-03-01), Watanabe et al.
patent: 5208776 (1993-05-01), Nasu et al.
patent: 5245576 (1993-09-01), Foss et al.
patent: 5262934 (1993-11-01), Price
patent: 5262999 (1993-11-01), Etoh et al.
patent: 5264743 (1993-11-01), Nakagome et al.
patent: 5276646 (1994-01-01), Kim
patent: 5297097 (1994-03-01), Etoh et al.
patent: 5307315 (1994-04-01), Oowaki et al.
patent: 5311476 (1994-05-01), Kajimoto et al.
patent: 5323354 (1994-06-01), Matsumoto et al.
patent: 5337284 (1994-08-01), Cordoba et al.
patent: 5347488 (1994-09-01), Matsushita
patent: 5351217 (1994-09-01), Jeon
patent: 5377156 (1994-12-01), Watanabe et al.
patent: 5602771 (1997-02-01), Kajigaya et al.
patent: 5699313 (1997-12-01), Foss et al.
patent: 5751643 (1998-05-01), Lines
patent: 5912564 (1999-06-01), Kai et al.
patent: 6055201 (2000-04-01), Foss et al.
patent: RE37593 (2002-03-01), Etoh et al.
patent: 6421295 (2002-07-01), Mao et al.
patent: 6483377 (2002-11-01), White et al.
patent: 6535424 (2003-03-01), Le et al.
patent: 0010137 (1980-04-01), None
patent: 0197505 (1986-10-01), None
patent: 2184902 (1984-10-01), None
patent: 2984902 (1984-10-01), None
patent: 2204456 (1988-05-01), None
patent: 56-062066 (1981-05-01), None
patent: SHOU/1981-62066 (1981-05-01), None
patent: 59-213090 (1984-12-01), None
patent: 62-021323 (1987-01-01), None
patent: 62-178013 (1987-08-01), None
patent: 62-189816 (1987-08-01), None
patent: 63-292488 (1988-11-01), None
patent: 01-185160 (1989-07-01), None
patent: 03-086995 (1989-08-01), None
patent: 30-23590 (1991-01-01), None
patent: WO86/04724 (1986-10-01), None
Aoki, Masakazu et al., “A 1.5V DRAM for Battery-Based Applications,”IEEE Journal of Solid-State Circuits, V. 24, No. 5, Oct. 1989, pp. 1206-1212.
Aoki, Masakazu et al., “New DRAM Noise Generation Under Half-VccPrecharge and its Reduction Using a Transposed Amplifier,”IEEE Journal of Solid-State Circuits, V. 24, No. 4, Aug. 1989, pp. 889-894.
Arimoto, Kazutami et al., “A 60-ns 3.3-V-Only 16-Mbit DRAM with Multipurpose Register,”IEEE Journal of Solid-State Circuits, V. 24, No. 5, Oct. 1989, pp. 1184-1189.
Arimoto, Kazutami et al., “A Speed-Enhanced DRAM Array Architecture with Embedded ECC,”IEEE Journal of Solid-State Circuits, V. 25, No. 1, Feb. 1990, pp. 11-17.
Asakura, Mikio, et al., “An Experimental 1-Mbit Cache DRAM with ECC,”IEEE Journal of Solid-State Circuits, V.25, No. 1, Feb. 1990, pp. 5-10.
Eldin, A.G., et al., “New Dynamic Logic and Memory Circuit Structures for BICMOS Technologies,”IEEE Journal of Solid-State Circuits, V. SC-22, No. 3, Jun. 1987, pp. 450-453.
Fujii, Syuso, et al., “A 50-μA Standby 1Mx1/256K×4 CMOS DRAM with High-Speed Sense Amplifier,”IEEE Journal of Solid-State Circuits, V. SC-21, No. 5, Oct. 1986, pp. 643-648.
Furuyama, Tohru, et al., “An Experimental 4-Mbit CMOS DRAM,”IEEE Journal of Solid-State Circuits, V. SC-21, No. 5, Oct. 1986, pp. 605-611.
Hori, Ryoichi, et al., “An Experimental 1 Mbit DRAM Based on HighS/NDesign,”IEEE Journal of Solid-State Circuits, V. SC-19, No. 5, Oct. 1984, pp. 634-640.
Gray, Paul R., et al., “MOS Operational Amplifier Design—A Tutorial Overview,”IEEE Journal of Solid-State Circuits, V. SC-17, No. 6, Dec. 1982, pp. 969-982.
Horiguchi, Masashi, et al., “A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier,”IEEE Journal of Solid-State Circuits, V. 25, No. 5, Oct. 1990, pp. 1129-1135.
Itoh, Kiyoo, “Trends in Megabit DRAM Circuit Design,”IEEE Journal of Solid-State Circuits, V. 25, No. 3, Jun. 1990, pp. 778-789.
Kimura, Katsutaka, et al., “A 65-ns 4-Mbit CMOS DRAM with a Twisted Driveline Sense Amplifier,”IEEE Journal of Solid-State Circuits, V. SC-22, No. 5, Oct. 1987, pp. 651-656.
Masuoka, Fujio, et al., “A 256-kbit Flash E2PROM Using Triple-Polysilicon Technology,”IEEE Journal of Solid-State Circuits, V. SC-22, No. 4, Aug. 1987, pp. 548-552.
Miyamoto, Jun-Ichi, et al., “An Experimental 5-V-Only 256-kbit CMOS EEPROM with a High-Performance Single-Polysilicon Cell,”IEEE Journal of Sol
Foss Richard C.
Gillingham Peter B.
Harland Robert F.
Lines Valerie L.
Hamilton Brook Smith & Reynolds P.C.
MOSAID Technologies Inc.
Riley Shawn
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