Dram bit lines

Details Dram bit lines Dram bit lines

2001-10-26

2004-04-06

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

C438S692000, C438S954000

Reexamination Certificate

active

06716715

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the manufacturing of DRAM devices. More specifically, the present invention relates to the forming of bit line structures in such memories.
2. Description of the Related Art
FIG. 1
partially and schematically illustrates in a top view, and
FIGS. 2A
,
2
B,
2
C in a cross-section view along respective axes A—A, B—B, and C—C, the structure of an elementary cell
1
of a DRAM of folded bit line type under manufacturing in a semiconductor substrate
2
, typically single-crystal silicon. A memory includes a plurality of such identical elementary cells
1
arranged in rows and columns. Each elementary cell
1
is formed in an active region
3
, generally rectangular, delimited in substrate
2
by insulating trenches
4
. Insulating trenches
4
are obtained by digging into substrate
2
, then filling the formed hollowings with an insulating material, generally silicon oxide (SiO
2
). In
FIG. 1
, the limit between active region
3
and insulating trenches
4
is illustrated by stripe-dot lines.
Four conductive lines WL
1
, WL
2
, WL
3
, and WL
4
cross the cell. Each of these lines, which are the word lines of the general memory device, is insulated from the underlying active areas
3
by an insulating layer
7
, typically silicon oxide. Their lateral walls are conventionally provided with spacers
8
. Two “active” word lines WL
2
and WL
3
cross the cell in its active region
3
. Active word lines WL
2
and WL
3
are common to all cells of a same row. The other two word lines WL
1
and WL
4
run over either side of active region
3
, that is, over insulating trenches
4
. Each of word lines WL
1
and WL
4
is one of the two active word lines of two different elementary cell rows, these two rows (not shown) being distinct from that containing elementary cell
1
.
After formation of word lines WL
1
, WL
2
, WL
3
, and WL
4
, heavily-doped regions
9
and
10
of a conductivity type opposite to that of substrate
2
have been formed by implantation/diffusion at the surface of active region
3
.
Active word lines WL
2
, WL
3
then form the gates of two MOS transistors of the same type, having common drain/source regions
9
and distinct source/drain regions
10
, each formed in the active region
3
between spacer
8
of the corresponding word line and the neighboring insulating trench
4
.
Substrate
2
(active region
3
and trenches
4
) and lines WL
1
, WL
2
, WL
3
, and WL
4
are altogether covered with a thick insulating layer
11
, typically silicon oxide. The upper surface of layer
11
is substantially planar. Layer
11
has been locally opened to at least partially expose the three semiconductor regions
9
and
10
. Contacts
5
and
6
, respectively with drain/source region
9
and each of source/drain regions
10
, result from the filling of the openings thus formed by means of a conductive material, typically metal, generally tungsten.
A bit line BL, common to the cells of a same column, runs over layer
11
above an insulating trench
4
separating two distinct cell columns. Bit line BL is encapsulated by an insulating structure
12
. Bit line BL is designed to contact drain/source region
9
via contact
5
.
Bit line BL may be formed before or after two memory points (capacitors) not shown, also formed on layer
11
, but each in contact with one of the two source/drain regions
10
via a contact
6
.
Be they formed after or before bit lines BL, the memory point structures must then take into account the presence or the subsequent forming thereof on a same level (the upper surface of layer
11
). This leads to managing manufacturing constraints, in particular alignment constraints, which complicate processes.
More specifically, protecting the structure against possible capacitive couplings or short-circuits, caused by misalignments of masks of formation of bit lines or memory points, limits the density of the obtained memory device.
Further, since the planar surface area available on layer
11
is limited, obtaining memory devices with capacitors having a sufficient capacitance imposes using memory points with a complex structure and/or limiting the device density.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a novel manufacturing method of a DRAM device, which reduces the preceding constraints.
The method is compatible with the forming of the DRAM on a same substrate as a logic circuit external to the memory.
The method includes two active word lines having a common drain/source region and having distinct source/drain regions contacting two memory points, including, after the forming of insulated conductive lines, the steps of:
a) depositing a first insulating layer;
b) depositing a second insulating layer, selectively etchable with respect to the first insulating layer;
c) etching the second insulating layer to only maintain it above the insulated conductive lines, at least inside and around an active region;
d) depositing and leveling a third thick insulating layer selectively etchable with respect to at least the second insulating layer;
e) opening the first and third insulating layers to at least partially expose the common drain/source region and an insulating trench;
f) depositing a conductive material to fill the previously-formed opening;
g) performing a chem-mech polishing of the entire structure; and
h) depositing a fourth insulating layer, selectively etchable with respect to the third insulating layer.
According to an embodiment of the present invention, step e) consisting of opening the first and third insulating layers to at least partially expose the common drain/source region and an insulating trench is implemented to open the first and third insulating layers to at least also partially expose the source/drain regions, the conductive material deposited at step f) being deposited to fill all the openings thus formed.
According to an embodiment of the present invention, step e) consisting of opening the first and third insulating layers to at least partially expose the common drain/source region and an insulating trench is preceded by the steps of:
i) opening the first and third insulating layers to at least partially expose the source/drain regions;
j) depositing a conductive material in the openings thus formed; and
k) performing a chem-mech polishing of the entire structure, whereby contacts are formed with the source/drain regions.
According to an embodiment of the present invention, step k) of chem-mech polishing is followed by the deposition of an additional insulating layer on the entire structure, step e) then consisting of successively opening the additional insulating layer and the first and third insulating layers to at least partially expose the common drain/source region and an insulating trench.
According to an embodiment of the present invention, step g) of chem-mech polishing of the entire structure, or step h) of deposition of the fourth insulating layer, selectively etchable with respect to the third insulating layer, is followed by the steps of:
l) opening the first and third insulating layers to at least partially expose the source/drain regions;
m) depositing a conductive material in the openings thus formed; and
n) performing a chem-mech polishing of the entire structure, whereby contacts are formed with the source/drain regions.
According to an embodiment of the present invention, step a) of deposition of the first insulating layer is preceded by the deposition of an additional insulating layer selectively etchable with respect to the filling material of underlying insulating trenches and with respect to the first insulating layer.
According to an embodiment of the present invention, the first and third insulating layers are made of silicon oxide (SiO
2
) and the second and fourth insulating layers as well as the additional insulating layer are made of silicon nitride (Si
3
N
4
).
According to an embodiment of the present invention, the memory cell is formed in a same substrate as logic circuits.
The prese

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