DRAM-based CAM cell with shared bitlines

Details DRAM-based CAM cell with shared bitlines DRAM-based CAM cell with shared bitlines

2006-03-21

2006-03-21

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S149000, C365S189030, C365S230050

Reexamination Certificate

active

07016211

ABSTRACT:
A CAM cell is disclosed that includes a comparator and two three-transistor (3T) DRAM cells connected to a pair of associated bit lines. Data is stored using intrinsic capacitance of each 3T DRAM cell, and is applied to the gate terminal of a pull-down transistor of the comparator. During refresh operations, inverted data values are written onto the bit lines, and subsequently written from the bit lines to the 3T DRAM cells. In ternary embodiments, an inverting refresh circuit is used to re-invert the inverted data values prior to being written to the 3T DRAM cells. In one embodiment, the 3T DRAM cells are cross-coupled to the bit lines, and the inverting refresh circuit transfers bits from one bit line to the other.

REFERENCES:
patent: 5189640 (1993-02-01), Huard
patent: 6353552 (2002-03-01), Sample et al.

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