DRAM-based CAM cell using 3T or 4T DRAM cells

Details DRAM-based CAM cell using 3T or 4T DRAM cells DRAM-based CAM cell using 3T or 4T DRAM cells

2001-03-22

2002-07-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050

Reexamination Certificate

active

06421265

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to content addressable memory (CAM) arrays. More specifically, the present invention relates to dynamic random-access-memory-based (DRAM-based) CAM arrays.
BACKGROUND OF THE INVENTION
Conventional read-write or “random access” memory (RAM) arrays include RAM cells arranged in rows and columns, and addressing circuitry that accesses a selected row of RAM cells using address data corresponding to the physical address of the RAM cells. That is, data words stored in the rows of conventional RAM cells are accessed by applying address signals to the RAM array input terminals. In response to each unique set of address signals, a RAM array outputs a data word that is read from a portion of the RAM array designated by the address.
Unlike conventional RAM arrays, content addressable memory (CAM) arrays include memory cells that are addressed in response to their content, rather than by a physical address within a RAM array. Specifically, a CAM array receives a data value that is compared with all of the data values stored in the rows of the CAM array. In response to each unique data value applied to the CAM array input terminals, the rows of CAM cells within the CAM array assert or de-assert associated match signals indicating whether or not one or more data values stored in the CAM cell rows match the applied data value. CAM arrays are useful in many applications, such as search engines.
Similar to conventional RAM devices, CAM devices can either be formed utilizing dynamic random access memory (DRAM) cells, in which data values are stored using capacitors, or formed utilizing static random access memory (SRAM) cells, in which data values are stored using bistable flip flops.
FIG.
1
(A) is a circuit diagram showing a conventional dynamic-based (DRAM-based) CAM cell
10
, which includes a pair of one-transistor (1T) DRAM cells
12
and
16
, and a four-transistor comparator circuit
14
made up of transistors Q
2
through Q
6
. DRAM cell
12
includes transistor Q
1
and a capacitor structure C
1
, which combine to form a storage node a that receives a data value from bit line BL
1
during write operations, and applies the stored data value to the gate terminal of transistor Q
2
of comparator circuit
14
. Transistor Q
2
is connected in series with transistor Q
3
, which is controlled by a data signal transmitted on inverted data line D
1
# (the “#” is used herein to designate complement), between a match line (MATCH) and a discharge line (DISCHARGE). A second DRAM cell
16
includes transistor Q
3
and a capacitor structure C
2
, which combine to form a storage node b that receives a data value from bit line BL
2
, and applies the stored data value to the gate terminal of transistor Q
4
of comparator circuit
14
. Transistor Q
4
is connected in series with transistor Q
5
, which is controlled by a data signal transmitted on inverted data line D
1
#, between the match line and the discharge line.
During a data write operation (or during the write phase of a refresh operation), a data value to be stored is written to dynamic storage nodes a and b by applying appropriate voltage signals (e.g., VCC or ground) on bit lines BL
1
and BL
2
, and then applying a high voltage signal on word lines WL
1
and WL
2
. The high voltage on word lines WL
1
and WL
2
turn on transistor Q
1
and Q
2
, thereby passing the voltage signals to dynamic storage nodes a and b. Because the voltage signals are stored using capacitors Cl and C
2
, the stored data value decays over time, thereby requiring refresh circuitry that periodically reads and rewrites (refreshes) the stored data value before it is lost.
The data value stored at storage nodes a and b is applied to the gate terminals of transistors Q
2
and Q
5
of comparator circuit
14
. Comparator circuit
14
is utilized to perform match (comparison) operations by precharging a match line M and transmitting an applied data value on data lines D
1
and D
1
# to the gate terminals of transistor Q
3
and Q
6
, respectively. A no-match condition is detected when match line M is discharged to ground through the signal path formed by transistors Q
2
and Q
3
, or through the signal path formed by transistors Q
5
and Q
6
. For example, when the stored data value at node a and the applied data value transmitted on data line D
1
# are both logic “1”, then both transistors Q
2
and Q
3
are turned on to discharge match line M to the discharge line (e.g., ground). When a match condition occurs, match line M remains in its pre-charged state (i.e., no signal path is formed by transistors Q
2
and Q
3
, or transistors Q
5
and Q
6
).
A problem with DRAM-based CAM cell
10
arises because the voltage signal (charge) stored at storage nodes a and b are directly applied to (shared with) bit lines BL
1
, and BL
2
, respectively, during read operations. Specifically, the charge stored at storage nodes a and b must be strong enough to pass through access transistors Q
1
and Q
4
and swing the voltage levels on bit lines BL
1
and BL
2
such that the stored data value can be read, for example, by a sense amplifier (not shown) connected to bit lines BL
1
and BL
2
. To provide this sufficient capacitance, capacitor structures C
1
and C
2
are often constructed using a special multi-layer polysilicon fabrication process that significantly increases fabrication time and expense. In addition, because the size of these capacitor structures is limited, the length of bit lines BL
1
and BL
2
must be limited to avoid excessively large bit line capacitances, thereby minimizing the number of CAM cells in each column of a DRAM-based CAM array. That is, the length and, hence, the capacitance of bit lines BL
1
and BL
2
increases with the number of DRAM CAM cells that are connected to these lines. Specifically, the voltage swing on a bit line is inversely proportional to bit line capacitance (i.e., length). When the bit line is too long (i.e., has too high of a capacitance), then the bit line voltage swing is too small to read. Because the length of the bit lines is limited, so too are the number of DRAM cells in each column that are connected to the bit line. By limiting the number of DRAM CAM cells in each column, the number of independent blocks of DRAM memory cells is increased, thereby requiring more space for control circuitry and increasing the overall size and cost of the DRAM CAM circuit. Finally, conventional DRAM-based CAM cell
10
is limited in that a read operation can be disturbed by a simultaneous match operation performed by comparator circuit
14
. When conventional DRAM cells
12
and
16
are read, the read data values are typically transmitted to associated bit lines during “quiet” periods in which switching noise in a DRAM array does not cause a loss of the read data values. However, by allowing simultaneous match operations during the read phase of the refresh operation, it is possible to lose the read data values.
FIGS.
1
(B) and
1
(C) are circuit diagrams showing conventional SRAM-based CAM cells
20
and
30
, respectively. In general SRAM-based CAM cells require more transistors than DRAM-based CAM cells, and are therefore typically much larger than DRAM-based CAM cell
10
(see FIG.
1
(A)). In addition, SRAM-based CAM arrays typically consume more power than DRAM-based CAM arrays. However, SRAM-based CAM cells overcome the charge sharing problems associated with DRAM-based CAM cells by utilizing bistable flip flops, which are able to store data values without the refresh operation required by DRAM cells. Further, even when a stored data value is read, the bistable flip flops transmit a current onto an adjoining bit line that, over time, generates enough charge to swing the bit line to indicate the stored data value. This current-over-time approach allows SRAM-based CAM arrays to include much longer bit lines (i.e., many more SRAM cells per bit line) because bit line swing can be achieved for any bit line length, given enough current and enough time.
FIG.
1
(B) shows a twelv

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