Dram array with local latches

Details Dram array with local latches Dram array with local latches

1996-10-29

1998-03-24

Zarabian, A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365 63, G11C 800

Patent

active

057320420

ABSTRACT:
A DRAM array has a row decoder means 2 and a column decoder 3 which are connected to a word line and a bit line of a cell matrix portion, respectively. The column decoder means 3 comprises a plurality of bit switches 44 and 46 for connecting a predetermined bit line to an output bus. Local latches 36 store data bits, each of the local latches provide for one group of bit lines 32 which is a unit of predetermined number of bit lines. The bit switches are arranged in a hierarchical structure, and connection between the bit line and the output bus is attained by two bit switches connected in series thereby load capacitance on the data lines 52 and 56 being able to be reduced. Data in respective local latches 36 is stored in the local buffer 74 in a predetermined order so that it can be burst transferred at a high speed.

REFERENCES:
patent: 5132928 (1992-07-01), Hayashikoshi
patent: 5208778 (1993-05-01), Kumanoya
patent: 5317539 (1994-05-01), Hoshino
patent: 5539700 (1996-07-01), Kawahara
patent: 5586078 (1996-12-01), Takase

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