DRAM architecture having distributed address decoding and timing

Details DRAM architecture having distributed address decoding and timing DRAM architecture having distributed address decoding and timing

1990-12-24

1992-10-27

Laroche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 365233, G11C 800

Patent

active

051595729

ABSTRACT:
A DRAM has both a distributed row address decode and a distributed timing control to generate required timing signals. A level of decoding is implemented within each of local row decoders to generate critical timing signals for each of a plurality of DRAM bit cell arrays. Word line signals from an output of each of the local row decoders are interleaved. The interleaved word line signals permit a high density DRAM semiconductor manufacturing process to utilize a differing pitch for each of a plurality of levels of interconnect. A first level of interconnect has a pitch which is significantly smaller than the pitch of a second interconnect level positioned above the first level of interconnect.

REFERENCES:
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4569036 (1986-02-01), Fujii et al.
patent: 4833656 (1989-05-01), Tobita
patent: 5043947 (1991-08-01), Oshima et al.
patent: 5119334 (1992-06-01), Fujii

Affiliated with

Also associated with

Rating

DRAM architecture having distributed address decoding and timing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM architecture having distributed address decoding and timing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM architecture having distributed address decoding and timing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-911073