DRAM

Details DRAM DRAM

2002-09-27

2004-09-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S149000

Reexamination Certificate

active

06798681

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of semiconductor memories. More specifically, the present invention relates to high-density DRAMs.
2. Discussion of the Related Art
Generally, a DRAM is formed of an array of elementary cells placed at the intersection of rows or word lines and of columns or bit lines.
As illustrated in
FIG. 1A
, such an elementary memory cell is formed of a capacitive memory point (capacitor) MP and of an element T for controlling the memory point, generally a MOS transistor. The gate of transistor T is connected to a word line WL of the cell. The source or drain of control transistor T is in contact with a first electrode of memory point MP, the other electrode or plate of which is common to all the cells of at least one column and is biased to a very steady plate voltage VP. The drain or the source of control transistor T is connected to a bit line BL common to all the cells of a column.
As an example, as illustrated in the top view of
FIG. 1B
, it will be considered in the following description that the memory cells are formed by groups of two in active areas A of a semiconductor substrate. Each active area A is rectangular, its largest side being vertical, along the column axis. Two MOS transistors of the same type and dimensions are formed in active area A to have a common drain or source region. A bit line contact BLC is formed on this common drain or source region. Contact BLC is shown at the center of active area A by a cross in a square. The gate of each transistor runs on one side of contact BLC. These gates are insulated lines represented by hatched horizontal areas. Each one forms the word line of a cell. Each end of active area A corresponds to a source or drain region of each transistor in contact with an electrode of a memory point MP. Each memory point MP is represented by a square indicating contact MPC with the source or drain region and, around contact MPC, by a parallelogram in dotted lines symbolizing the capacitor surface.
Designating by F the smallest possible dimension for a conductive line, which is also called the minimum rule since it corresponds to a drawing rule imposed to the designer for a manufacturing technology, square F
2
of minimum rule F then being the minimum surface area or unity surface area of a pattern, elementary cells with a surface area four times as large as the unity surface area (4F
2
) could theoretically be formed. In practice, the cells have a greater dimension generally on the order of eight times the unity surface area (8F
2
).
To form DRAMs based on elementary cells identical to those in
FIG. 1A
, it has first been provided to repeat an elementary pattern formed of an elementary memory cell.
FIG. 2A
schematically illustrates the arrangement of the DRAM thus obtained. In such an array, any intersection of a row WL
l
, WL
l+1
, WL
l+2
and of a column BL
j
, BL
j+1
, BL
j+2
, BL
j+3
includes an elementary memory cell represented by a point. Each bit line BL
j
, BL
j+1
, BL
j+2
, BL
j+3
is connected to an input of a respective sense amplifier SA
j
, SA
j+1
, SA
j+2
, and SA
j+3
. To enable reading, a second input of each amplifier SA is connected to a reference line RBL.
As illustrated in
FIG. 2B
, the forming in integrated form, in a semiconductor substrate of such an array then consists of repeating in the row (horizontal) direction as well as in the column (vertical) direction the structure described in relation with FIG.
1
B.
A problem in this type of structure is the placing of sense amplifiers which require a width greater than that of a column. Another problem is the fact that the reference line(s) are independent from the bit lines and exhibit a noise which is not correlated with the noise therein.
To overcome these problems, a second type of memory such as illustrated in
FIG. 3A
has been provided, the elementary pattern of which extends over two rows and two columns and only includes two columns. Two adjacent bit lines of a same pattern respectively receive a signal and its complement. The two cells of a pattern are arranged so that each of the two rows and each of the two columns of the elementary pattern includes a single cell. As compared to an array of the first type described in relation with
FIG. 2A
, a row or a column of same dimension of an array of the second type includes half as many cells, an intersection out of two with a line or a row, respectively, being empty. Further, in the vertical direction, two adjacent patterns are arranged symmetrically. Thus, the word lines are arranged in order WL
0
, WL
1
, WL
3
, WL
2
. . . WL
2k
, WL
2k+1
, WL
2k+3
, WL
2k+2
. . .
FIG. 3B
illustrates, in top view, the forming according to the technological process defined in
FIG. 1B
of a memory of the second type. More specifically,
FIG. 3B
illustrates the forming of the array portion including the intersections of the four rows WL
2k
, WL
2k+1
, WL
2k+3
, WL
2k+2
and of the four columns BL
t
, {overscore (BL)}
t
, BL
t+1
, and {overscore (BL)}
t+1
of FIG.
3
A.
The elementary cells of a same column are aligned. However, from a given column BL
t
to the next one {overscore (BL)}
t
, the active areas in each of which are formed two cells are shifted so that word lines WL
2k+1
, WL
2k+3
of column BL
t
can cross the next column {overscore (BL)}
t
above an insulating area separating two active areas.
As illustrated in
FIG. 3C
, to enable passing between two active areas of two conductive lines WL
2k+1
, WL
2k+3
, while minimizing the bulk, rows (word lines) WL
2k
, WL
2k+1
, WL
2k+3
, WL
2k+2
are given a zigzag shape. With this arrangement, the elementary cell of a memory of the second type exhibits a theoretical surface area of eight times the unity surface area (8F
2
), in practice from ten to fourteen times said surface area.
Upon access to a cell of a given row WL
2k+1
at the intersection with a given bit line BL
t
, the neighboring bit line {overscore (BL)}
t
for which the considered row WL
2k+1
includes no cell is used as a reference line. Conversely, for the preceding row WL
2k
or the next row WL
2k+2
, upon access to the cell of this row placed at the intersection with bit line {overscore (BL)}
t
, the neighboring bit line BL
t
is used as a reference bit line. Thus, each elementary column pair BL
t
, {overscore (BL)}
t
or BL
t+1
, {overscore (BL)}
t+1
of the array is connected to a sense amplifier SA
t
, SA
t+1
. There thus is one sense amplifier for two columns and no longer one per column as in the first type of memory.
Such a use as a reference bit line of a neighboring line enables in the first place recovering the surface area used in a memory of the first type by the reference line to form memory cells. In the second place, to form sense amplifiers of the same dimension, the space occupied by two columns instead of one in the case of an array of the first type is now available. Further, the number of sense amplifiers is reduced by half as compared to a memory of the first type. The column length can then be increased. In the third place, the fact of forming bit line BL
t
, {overscore (BL)}
t
, BL
t+1
, {overscore (BL)}
t+1
and its corresponding reference line {overscore (BL)}
t
, BL
t
, {overscore (BL)}
t+1
, BL
t+1
in a same array enables them to have a correlated noise. The densities and access performances of memories of the second type are thus improved with respect to memories of the first type.
A problem with this type of structure is that, as technology advances, as the dimensions of elementary cells and of the metallizations forming the word lines are reduced, it becomes impossible to form zigzag lines such as shown in
FIG. 3C. A
design of the type of that in
FIG. 3B
must thus be used again and the theoretical space gain resulting from the reduction in line dimensions is lost.
SUMMARY OF THE INVENTION

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