Drain source protected MNOS transistor and method of manufacture

Details Drain source protected MNOS transistor and method of manufacture Drain source protected MNOS transistor and method of manufacture

1976-08-16

1977-10-11

Wojciechowicz, Edward J.

357 54, 357 6, H01L 2978, H01L 2934, H01L 4902

Patent

active

040539172

ABSTRACT:
An improved drain source protected MNOS transistor is realized by means of a fabrication technique that permits independent control of memory and nonmemory parameters. Self alignment of memory regions during fabrication is achieved by using nitride masking for gate oxidation. Independent control of memory and nonmemory parameters derives from a device configuration in which protected regions consist exclusively of gate oxide and silicon nitride is present only in the memory regions. Transistor radiation hardening is also achieved by elimination of the nitride layer above the device's thin silicon dioxide regions.

REFERENCES:
patent: 3836894 (1974-09-01), Cricchi

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