Drain-extended MOS ESD protection structure

Details Drain-extended MOS ESD protection structure Drain-extended MOS ESD protection structure

2003-07-14

2004-10-12

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000, C361S118000

Reexamination Certificate

active

06804095

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of semiconductor integrated circuits, and is more specifically directed to techniques for protecting integrated circuits from damage caused by electrostatic discharge.
Modern high-density integrated circuits are known to be vulnerable to damage from the electrostatic discharge (ESD) of a charged body (human or otherwise) as it physically contacts an integrated circuit. ESD damage occurs when the amount of charge exceeds the capability of the conduction path through the integrated circuit. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting (e.g., in the metal-oxide-semiconductor, or MOS, context).
It is often difficult to analyze the ESD vulnerability of a given integrated circuit, because the charge versus time characteristics of ESD events vary quite widely among the various sources of ESD. In fact, the ESD protection of modern integrated circuits is characterized according to multiple models, each of which are intended to model a type of ESD. The Human Body Model (HBM) models discharge of a charged human contacting an integrated circuit, and is realized by a 150 pF capacitance discharging into the integrated circuit within about 100 nsec. The Machine Model (MM) models discharge from metal objects such as test and manufacturing equipment, and generally uses a higher capacitance with lower internal resistance than the HBM, resulting in even faster discharge times. The Charged Device Model (CDM) models a discharge from a charged integrated circuit to ground, rather than a discharge to the integrated circuit. These differences in discharge characteristics and polarity manifest themselves in different failure manifestations within the integrated circuit; indeed the conduction may follow different paths within the device.
To avoid damage from ESD, modern integrated circuits incorporate ESD protection devices at each external terminal. ESD protection devices generally operate by providing a high capacity conduction path, so that the brief but massive ESD charge may be safely conducted away from structures that are not capable of handling the event. In some cases, ESD protection is inherent to the particular terminal, as in the case of a power supply terminal which may provide an extremely large p-n junction capable of conducting the ESD charge. Inputs and outputs, on the other hand, typically have a separate ESD protection device added in parallel to the functional terminal. The ideal ESD protection device turns on quickly in response to an ESD event, with large conduction capability, but remains off and presents no load during normal operation.
Examples of ESD protection devices are well known in the art. In the case of MOS technology, an early ESD protection device was provided by a parasitic thick-field oxide MOS transistor that was turned on by and conducted ESD current, as described in U.S. Pat. No. 4,692,781 and in U.S. Pat. No. 4,855,620, both assigned to Texas Instruments Incorporated and incorporated herein by this reference. As the feature sizes of MOS integrated circuits became smaller, and with the advent of complementary MOS (CMOS) technology, the most popular ESD protection devices utilized a parasitic bipolar device to conduct the ESD current, triggered by way of a silicon-controlled-rectifier (SCR) structure, as described in Rountree et al., “A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes”, 1988 EOS/ESD
Symposium
, pp. 201-205, incorporated herein by this reference, and in U.S. Pat. No. 5,012,317 and U.S. Pat. No. 5,307,462, both assigned to Texas Instruments Incorporated and also incorporated herein by this reference.
It has been observed that changes in integrated circuit manufacturing technology often necessitate changes in the ESD protection scheme, generally because the process changes alter the ability of the ESD protection devices to operate. The silicide cladding of junctions and the incorporation of shallow trench isolation (STI) have been observed to reduce the gain of the parasitic bipolar device in the SCR protection scheme, preventing proper triggering and conduction. The effects of these process changes are exacerbated by the continuing trend toward smaller device feature sizes, both laterally and vertically, rendering the devices ever more fragile to ESD.
However, the continued progression toward smaller device sizes has not, in many cases, relaxed the voltage requirements of integrated circuit terminals. For example, a modern manufacturing process fabricates transistors having 0.18&mgr; channel lengths, with a gate dielectric thickness of 7 nm or less, for use in integrated circuits that must still tolerate operating voltages of up to 7 volts at input/output terminals. Many integrated circuits are also required to have “failsafe” inputs and outputs, meaning that the terminal cannot be clamped to any power supply rail, so that large currents are not conducted from terminal voltages when the device is in an “off” state. The “failsafe” constraint is especially important in multi-voltage systems in which the inputs and outputs are power sequenced.
The high operating voltage and failsafe design constraints have been addressed through the use of drain-extended MOS transistors (referred to as DE, DEMOS, or DENMOS in the case of n-channel devices). A conventional DE transistor has its drain region located within a well of the same conductivity type; for example, in the n-channel case, the n-type drain region is placed within a relatively lightly-doped n-type well. The increased drain-to-substrate junction area provided by the well, along with the reduced dopant concentration at the drain-to-substrate junction, greatly increases the junction breakdown voltage, permitting high voltage operation of the transistor while tolerating voltage excursions at the drain that can occur in the absence of a clamp. DEMOS transistors also enable the use of thinner gate oxide, because the voltage drop across the depletion region of the well reduces the electric field at the drain-side edge of the gate oxide, and thus reduces the number of channel “hot” carriers that are produced. This reduction in “hot” carrier effects, specifically threshold voltage shift, enables the construction of reliable transistors with extremely thin gate oxides. DEMOS devices also present high output impedance, which is especially attractive in using the device in analog circuits. DEMOS transistors are therefore very attractive for use at input/output terminals of modern integrated circuits.
It has been observed, however, that DEMOS devices themselves provide very poor inherent ESD protection. Referring to
FIG. 1
a
, plot
2
illustrates source-drain current versus drain-to-source voltage for DENMOS transistor
6
(
FIG. 1
b
), with the gate grounded as shown in
FIG. 1
b
. Plot
2
represents actual measurements of transistor
6
, of drain-extended construction to have an effective channel length of 0.64&mgr; and a channel width of about 50&mgr;, measured from a sequence of 100 nsec pulses of increasing voltage applied to the drain of transistor
6
. As shown by plot
2
of
FIG. 1
a
, drain avalanche breakdown of transistor
6
occurs at about 13 volts drain-to-source-voltage. Unlike conventional ESD protection devices, however, there is no parasitic lateral npn bipolar conduction in transistor
6
, and thus no “snapback” region in characteristic plot
2
(as shown by the ideal plot
2
′ in
FIG. 1
a
). Instead, a relatively high “on” resistance of about 20 ohms is evident, with conduction continuing until about 17 volts, at which point thermal runaway causes device failure (evident by the knee in plot
2
at that point). While gate-coupled DENMOS devices have exhibited some snapback in their characteristic, it has been found that the failure current (i.e., the thermal runaway point in the characteristic) does not scale with chan

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