DQS signaling in DDR-III memory systems without preamble

Details DQS signaling in DDR-III memory systems without preamble DQS signaling in DDR-III memory systems without preamble

2008-03-11

2008-03-11

Phung, Anh (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S052000

Reexamination Certificate

active

07342815

ABSTRACT:
A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

REFERENCES:
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patent: 6838907 (2005-01-01), Artsi
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patent: 7208973 (2007-04-01), Kwon
patent: 2003/0080774 (2003-05-01), Funaba
patent: 2004/0100837 (2004-05-01), Lee

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