DQPSK mapping circuit

Details DQPSK mapping circuit DQPSK mapping circuit

1997-10-06

2000-06-13

Pham, Chi H.

Pulse or digital communications

Receivers

Angle modulation

329310, H03D 322, H04L 2722

Patent

active

060758279

ABSTRACT:
A DQPSK mapping circuit is disclosed which comprises: a parallel decoding circuit having inputs for decoding first to 2Nth bits of input data and one symbol period prior I and Q data which are prior by one symbol period from the present decoding cycle thereof through the inputs and outputting serial first to Nth I and Q data of the present decoding period in parallel, N is a natural number; and a FF circuit for supplying the Nth I and Q data to the inputs as the one symbol period prior I and Q data in the succeeding decoding cycle of the parallel decoding circuit. The parallel decoding circuit may comprise first to Nth decoders, an Mth decoder out of the first to Nth decoders decoding 2Mth bit and (2M-1)th bits of the input data and outputs of (M-1)th decoder, M being a natural number and M.ltoreq.N, wherein the first decoder decodes the one symbol period prior I and Q data and the first and second bits of the input data.

REFERENCES:
patent: 4714913 (1987-12-01), Cohen
patent: 5717394 (1998-02-01), Schwartz et al.

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