DQPSK delay detection circuit that produces stable clock signal

Details DQPSK delay detection circuit that produces stable clock signal DQPSK delay detection circuit that produces stable clock signal

1993-11-23

1995-10-31

Chin, Stephen

Pulse or digital communications

Synchronizers

Self-synchronizing signal

375331, H04L 702, H03D 322

Patent

active

054636647

ABSTRACT:
A DQPSK delay detection circuit is provided that can securely reproduce stable clock signal. An absolute value circuit ABS(14) calculates an absolute value of I signal. An absolute value circuit ABS(15) calculates an absolute value of Q signal. Subtraction circuit(16) generates a P signal according to the difference between the absolute values of I signal and Q signal. Zero-cross detection circuit(11) detects zero-cross timing of the P signal to input it as a timing signal to the DPLL(64). The zero-cross timing of the P signal can be detected even when the data pattern of I or Q signal makes it impossible to detect the zero-cross timing from I and Q signal. Because the zero-cross timing of the P signal has a variation less than that of the zero-cross timing determined from I or Q signal, it is becomes possible to reproduce stable clock signals and in turn reliability of data demodulation can be improved.

REFERENCES:
patent: 4879728 (1989-11-01), Tarallo
patent: 4896336 (1990-01-01), Henely et al.
Configuration and Characteristics of .pi./4-Shift QPSK Bandbase Delay Detector, Satoshi Denno et al., Autumn National Convention, B-300, 1990, Institute of Electronics, Information and Communication Engineers.

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