DQPSK delay detection circuit

Details DQPSK delay detection circuit DQPSK delay detection circuit

1993-06-29

1995-01-03

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

329304, H04L 2722

Patent

active

053793234

ABSTRACT:
A DQPSK delay detection circuit includes a semi-synchronous detector synchronously detecting an input signal to obtain two demodulated signals, a low-pass filter for extracting a baseband signal from the demodulated signals, an A-D convertor sampling the baseband signal by a clock signal with a frequency 32 times higher than a symbol rate frequency and converting them to digital values with a predetermined number of quantization bits, a clock pulse generator generating clock signals synchronized with the baseband signal and having a frequency equal to and two times as high as the symbol rate frequency with a phase adjusted in accordance with a change of an eye pattern of an output of the A-D convertor, a data delay unit delaying the output of the A-D convertor by a time equivalent to one time slot according to a clock signal synchronized with the baseband signal and having a frequency equal to the symbol rate frequency, an operation unit generating signals I and Q from the output of the A-D convertor and a one-time-slot-before output of the A-D convertor delayed by the data delay unit according to a clock signal synchronized with the baseband signal and having a frequency equal to the symbol rate frequency, and a judging unit demodulating an in-phase component signal and orthogonal component signal from the signals I and Q and performing parallel-serial conversion to output data.

REFERENCES:
patent: 4438524 (1984-03-01), Muilwijk
patent: 4847869 (1989-07-01), Labedz et al.
patent: 4879728 (1989-11-01), Tarallo

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