Doubled stacked trench capacitor DRAM and method of fabricating

Details Doubled stacked trench capacitor DRAM and method of fabricating Doubled stacked trench capacitor DRAM and method of fabricating

1991-04-18

1994-10-11

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437 54, 437 47, 437 48, H01L 2700

Patent

active

053547012

ABSTRACT:
A process of fabricating a double stacked trench capacitor DRAM cell and resulting DRAM cell is described. The process begins by forming a trench in a semiconductor substrate. A first insulating layer is formed on the top surface of the substrate and on the sidewalls and bottom of the trench. A first contact opening is formed in the first insulating layer. A first polysilicon layer is formed and patterned to overlay the trench surface and a portion on the surface that extends into the contact opening. An insulating layer is formed over the first polysilicon layer. A second polysilicon layer is formed and patterned over the first polysilicon layer. An insulating layer is formed over the second polysilicon layer. A second contact opening is formed in the first insulating layer. A third polysilicon layer is formed over the second polysilicon layer and a portion extending into the second contact opening. A pair of FETs are formed with the drain regions in contact with the respective first and third polysilicon layers through the contact openings. A metallurgy system is formed wherein the gate electrodes of the FETs are joined to word lines, and the source regions are joined to bit lines of the supporting device.

REFERENCES:
patent: 4877750 (1989-10-01), Okumura

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