Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Warping of semiconductor substrate
Reexamination Certificate
1999-01-05
2002-05-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Warping of semiconductor substrate
C257S208000
Reexamination Certificate
active
06383892
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to silicon junction devices formed in silicon on insulator (SOI) technology.
2. Background Description
Typical prior art bulk silicon such as diodes, field effect transistors (FETs) and bipolar transistors formed on a silicon wafer are subject to parasitic effects resulting from other bulk devices in close proximity and from vertical structural asymmetry. These parasitic effects include voltage limitations and cross-device interference.
Consequently, typical bulk semiconductor processes, especially FET processes that include both p-type FETs (PFETs) and n-type FETS (NFETs) and commonly referred to as CMOS, require dedicated structures to localize and reduce parasitic effects. These specialized structures include providing surface diffusions referred to as guard rings, individual doped wells (N-wells and/or P-wells) and including a buried insulator.
Discrete devices, i.e., individually formed and packaged transistors or diodes, are normally free from these parasitic effects. One example of such discrete device is a discrete JFET. A discrete JFET may be formed in a doped silicon bar by forming contacts at opposite ends of the bar and a diffusion ring of an opposite dopant type therebetween. However, these discrete devices have limited applications and do not have any of the advantages of monolithic circuit integration.
Thus, there is a need for individually isolated semiconductor devices that may be integrated into a single circuit on a single chip.
SUMMARY OF THE INVENTION
It is therefore a purpose of the present invention to improve silicon device isolation.
It is another purpose of the present invention to improve integrated circuit device isolation.
It is yet another purpose of the present invention to improve integrated circuit device isolation without impairing device density.
The present invention is an integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provide controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to facilitate creating multiple vertically stacked isolated devices.
Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation styles.
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Chardurjian Mark
International Business Machines - Corporation
McGuireWoods LLP
Niebling John F.
Stevenson André C
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