Double-sided integrated circuit chips

Details Double-sided integrated circuit chips Double-sided integrated circuit chips

2011-08-02

2011-08-02

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S622000, C438S624000, C257SE25027

Reexamination Certificate

active

07989312

ABSTRACT:
A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

REFERENCES:
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4939568 (1990-07-01), Kato et al.
patent: 5825696 (1998-10-01), Hidaka et al.
patent: 5889302 (1999-03-01), Liu
patent: 6166438 (2000-12-01), Davidson
patent: 6355501 (2002-03-01), Fung et al.
patent: 6410371 (2002-06-01), Yu et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6762076 (2004-07-01), Kim et al.
patent: 6812127 (2004-11-01), Oshima et al.
patent: 6815278 (2004-11-01), Ieong et al.
patent: 6821826 (2004-11-01), Chan et al.
patent: 6830962 (2004-12-01), Guarini et al.
patent: 6943067 (2005-09-01), Greenlaw
patent: 7320115 (2008-01-01), Kuo
patent: 2003/0129829 (2003-07-01), Greenlaw
patent: 2004/0048459 (2004-03-01), Patti
patent: 2004/0105300 (2004-06-01), Chuang et al.
patent: 2004/0144979 (2004-07-01), Bhattacharyya
patent: 2004/0188819 (2004-09-01), Farnworth et al.
patent: 2005/0070077 (2005-03-01), Guarini et al.
patent: 2005/0093104 (2005-05-01), Ieong et al.
patent: 2005/0269680 (2005-12-01), Hsuan
patent: 2005/0275017 (2005-12-01), Pozder et al.
patent: 2006/0068557 (2006-03-01), Ochimizu et al.
patent: 2006/0226491 (2006-10-01), Gauthier, Jr. et al.
Notice of Allowance (Mail Date Oct. 8, 2009) for U.S. Appl. No. 11/383,586, filed May 16, 2006, First Named Inventor Kerry Bernstein, Confirmation No. 7897.
Office Action (Mail Date: Nov. 19, 2010) for U.S. Appl. No. 11/939,612, filed Nov. 14, 2007; Confirmation No. 6312.
U.S. Appl. No. 11/939,612, filed Nov. 14, 2007, First Named Inventory Kerry Bernstein et al.; Confirmation No. 6312.

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