Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-12-14
2002-04-16
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S261000, C174S262000, C174S263000, C257S698000, C361S768000
Reexamination Certificate
active
06373000
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a double-sided printed wiring board (i.e., double-sided circuit board, hereinafter sometimes abbreviated as double-sided PWB) of which the wiring conductors on both sides are electrically connected with solder having a metal powder dispersed therein, a multilayer printed wiring board (i.e., multilayer wiring board, hereinafter sometimes abbreviated as ML-PWB) comprising the same, and a process for producing the double-sided PWB.
BACKGROUND OF THE INVENTION
With the recent tendencies for electronic equipment to have a smaller size and higher performance, it has been demanded for semiconductor devices constituting electronic equipment and ML-PWBs for mounting the devices to have reduced size and thickness, higher performance and higher reliability. To meet these demands, pin insertion mount package is being displaced by surface mount package, and, in recent years, a surface mount technology called bare chip mount has been under study, in which non-packaged (bare) semiconductor elements are directly mounted on a PWB.
Further, the increasing number of pins of semiconductor elements to be mounted has increased the necessity of stacking a plurality of PWBs. An ML-PWB can be produced by a build up method comprising alternately building up, on one or both sides of a substrate, insulating layers of a photosensitive resin and conductor layers formed by plating or deposition. The build up method is disadvantageous in that the production process is complicated and involves many steps, the yield is low, and much time is required.
In bare chip mounting, on the other hand, because silicon chips having a thermal expansion coefficient of 3 to 4 ppm/° C. are directly mounted on a PWB having a thermal expansion coefficient of 10 to 20 ppm/° C. with an adhesive, stress develops due to the difference in thermal expansion to impair the reliability. The stress also causes cracks in the adhesive, which results in reduction of moisture resistance. In order to relax the stress, it has been practiced to use an adhesive having a reduced elastic modulus thereby to disperse the stress imposed. However, connection reliability achieved by such conventional techniques is still insufficient. It is indispensable for securing further improved reliability to diminish the thermal expansion coefficient of the PWB itself.
Under these circumstances, the present inventors previously proposed (1) a low-expansion double-sided PWB which comprises an insulating layer of an organic high molecular weight resin having a metal core and a wiring conductor provided on each side of the insulating layer, the wiring conductor on both sides being electrically connected via through-holes and (2) a low-expansion ML-PWB which comprises a plurality of the double-sided PWBs integrally laminated with each other via an adhesive layer interposed between every adjacent PWBs, the adhesive layer having through-holes at prescribed positions in contact with the wiring conductors of the adjacent upper and lower double-sided PWBs, and the through-holes containing a conductor made of solder by which the wiring conductors of the upper and the lower double-sided PWBs are electrically connected (see Japanese patent application No. 9-260201).
It has turned out that the above-mentioned double-sided PWB, which has the wiring conductors on both sides thereof electrically connected through via-holes, develops cracks at the corners in a cycling test, which will lead to an electrical connection failure. Further, where a plurality of the above-described double-sided PWBs are superposed on each other to obtain an ML-PWB, the adhesive layer connecting the upper and the lower PWBs is not allowed to have the solder conductors provided at the positions corresponding to the through-holes of the upper and the lower double-sided PWBs, which limits the freedom of wiring design.
To solve these problems, the inventors proposed a low-expansion double-sided PWB having high reliability and high freedom of wiring design, in which the wiring conductors on both sides thereof are electrically connected through via-holes filled with a conductor made of solder (as of yet unpublished Japanese Patent Application No. 9-199690). According to this technique, however, where the insulating layer has a large thickness in relation to the diameter of the via-holes, i.e., where the via-holes have a high aspect ratio, the solder-filled via-holes tend to undergo permanent deformation due to the stress accumulated in a cycling test, which will lead to a failure to connect to the wiring conductors.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a double-sided PWB (double-sided circuit board) and an ML-PWB (multilayer wiring board) comprising the double-sided PWBs in which a conductor made of solder is prevented from deformation in a cycling test so that high connection reliability can be maintained.
Another object of the present invention is to provide a process for producing the double-sided PWB.
The present inventors have conducted extensive study seeking a double-sided PWB of which the conductor made of solder is prevented from deformation in a cycling test. As a result, they have found that the above objects are accomplished by the following invention.
The invention provides, in its first aspect, a double-sided PWB comprising an insulating layer made of an organic high molecular weight resin having on each side thereof a wiring conductor, wherein the wiring conductors on both sides are electrically connected through via-holes filled with a conductor made of solder having a metal powder dispersed therein.
The invention provides, in its second aspect, an ML-PWB which comprises a plurality of the double-sided PWBs integrally laminateded with each other via an adhesive layer interposed between every adjacent PWBs, the adhesive layer having through-holes at prescribed positions in contact with the wiring conductors of the adjacent upper and lower double-sided PWBs and the through-holes being filled with a conductor made of solder by which the wiring conductors of the upper and the lower double-sided PWBs are electrically connected.
The invention provides, in its third aspect, a process for producing the double-sided PWB comprising the steps of:
(1) providing at least one through-hole in an insulating layer comprising an organic high molecular weight resin;
(2) pressing a mixture of a metal powder and a solder powder at a predetermined mixing ratio into the through-hole;
(3) melting the solder powder in the insulating layer into which the metal powder and the solder powder are pressed in the through-hole, under pressure, to fill the through-hole with a conductor of solder having the metal powder dispersed therein; and
(4) laminating both sides of the insulating layer from step (3) with copper foil and melting the conductor of solder.
According to the invention, plastic deformation of the solder conductor is prevented by the hard metal powder dispersed in the soft solder thereby to secure sufficient strength while maintaining low connection resistance. Thus, deformation of the solder conductor in a cycling test can be suppressed, and high connection reliability can be retained.
In a highly preferred embodiment of the invention, the insulating layer contains an Ni—Fe-based alloy foil as a core. According to this embodiment, the presence of one low-expansion Ni—Fe-based alloy layer (core) per two wiring conductor layers brings the thermal expansion coefficient of the double-sided PWB as a whole very close to that of silicon even where the wiring conductors are made of copper. The lowered thermal expansion coefficient of the double-sided PWB secures extremely high reliability even in bare chip mount.
REFERENCES:
patent: 4950843 (1990-08-01), Hirota
patent: 5451721 (1995-09-01), Tsukada et al.
patent: 6159586 (2000-12-01), Inoue et al.
patent: 6258449 (2001-07-01), Nagasawa et al.
patent: 61-212096 (1986-09-01), None
patent: 5-259600 (1993-10-01), None
patent: 6-97665 (1994-04-01), None
patent: 6-268381 (1994-09-01), None
Inoue Yasushi
Kaneto Masayuki
Nagasawa Megumu
Nakamura Kei
Okeyui Takuji
Nitto Denko Corporation
Paladini Albert W.
Sughrue & Mion, PLLC
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