Double side stack packaging method

Details Double side stack packaging method Double side stack packaging method

2006-09-26

2006-09-26

Pham, Thanhha (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S112000

Reexamination Certificate

active

07112473

ABSTRACT:
In a double side stack packaging a plurality of chips, a hole is formed in a substrate. A first chip is attached to a bottom surface of the substrate by using a thermo compression and is electrically interconnected to terminals formed at sidewall of the hole using a wire bonding. Next, an epoxy is coated on the substrate and the first chip and a first heat spreader is installed thereon and then the epoxy is cured. Thereafter, a second chip is attached to a top surface of the substrate by using the epoxy and is electrically interconnected to terminals formed on the substrate using the wire bonding. And then, an encapsulation resin is coated on the substrate and the first chip and a second heat spreader is installed thereon and then the epoxy is cured.

REFERENCES:
patent: 6093969 (2000-07-01), Lin
patent: 6265782 (2001-07-01), Yamamoto et al.
patent: 6300163 (2001-10-01), Akram
patent: 6559525 (2003-05-01), Huang
patent: 6815251 (2004-11-01), Akram et al.
patent: 2003/0030151 (2003-02-01), Morozumi
patent: 2003/0064547 (2003-04-01), Akram et al.

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