Double-sampling pseudo-3-path bandpass sigma-delta modulator

Details Double-sampling pseudo-3-path bandpass sigma-delta modulator Double-sampling pseudo-3-path bandpass sigma-delta modulator

1999-02-01

2001-01-09

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

Reexamination Certificate

active

06172631

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a bandpass sigma-delta modulator outputting a bit stream. More particularly, this invention relates to a bandpass sigma-delta modulator that has a double-sampling rate, thereby reducing by half both the number of required amplifiers and the mismatch problems between capacitors. Thus, higher frequency operation can be easily achieved without additional analog circuits.
2. Description of Related Art
In modern wireless communication systems, progress in CMOS technology has made it possible for applications to utilize not only the digital signal process in the baseband, but also the analog signal process in the intermediate frequency (IF) band and the radio frequency (RF) band. Due to the robustness and precision of digital signal processing, however, more functions in the analog domain are being replaced with their equivalent digital counterparts.
In the receiver architectures, IF digitization or performing analog to digital conversion in the IF band overcomes the difficulties of single chip implementation in the superheterodyne receiver, and the problems of DC offset, flicker noise, phase error and I/Q gain mismatch in the direct-conversion receiver.
The bandpass delta-sigma (&Dgr;&Sgr;) modulator provides a versatile method of performing analog to digital conversion in the IF. In prior art, the central frequency is usually set as ¼ of sampling rate, and the circuit performance limits the value of sampling rate. Generally, the IF is limited to 5 MHz, which is significantly lower than the standard IF of 10.7 MHz or 21.4 MHz.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a modulator circuit to raise the central frequency with a double sampling rate in which only one amplifier is needed to realize a 2
nd
-order system.
It is an advantage of the invention that the equivalent sampling rate of the circuit is double the sampling rate corresponding to the prior art. In addition, it is not necessary to further enhance the performance of the analog circuit, e.g., by the annexation of extra requirements including clock rate, opamp settling time, do gain, etc. Only one amplifier is required to build a 2
nd
-order system applying the pseudo-3-path method of this invention; thus, the number of amplifiers required by the 2
nd
-order system of the prior art is reduced. Besides, the forming of circuits by CMOS technology in this invention is of great benefit to the integration of circuits.
First, a double sampling pseudo-3-path bandpass filter is provided in this invention. Then, the above filter is applied to a bandpass delta-sigma modulator to exercise the function of doubling sampling.
Although illustrated and described herein as embodying a double sampling pseudo-3-path bandpass filter and a bandpass delta-sigma modulator, this invention is not intended to be limited to the details shown. Various modifications and structure changes may be made therein without departing from the spirit of the invention and within the scope and the range of equivalents of the claims.


REFERENCES:
patent: 5982315 (1999-11-01), Bazarjani et al.
Shen-Iuan Liu; Chien-Hung Kuo; Ruey-Yuan Tsai; Jingshown Wu ; A double-sampling pseudo-two-path bandpass &Dgr;&Sgr; modulator, IEEE Journal of Solid-State Circuits, vol.: 35 Issue: 2, Feb. 2000; pp.: 276-280.
A second-order double-sampled delta-sigma modulator using addivtive-error switching; Bumas et al.; IEEE Journal of Solid-State Circuits; vol.: 31 Issue: 3, Mar. 1996; pp.: 284-293.
Yang et al., A Novel Double Sampling Technique For Delta-Sigma Modulators, Circuits and Systems, 1994., Proceedings of the 37thMidwest Symposuim on Published: 1994., vol. 2, pp.: 1187-1190 vol. 2.
Bang-Sup Song, A Fourth-Order Bandpass Delta-Sigma Modulator With Reduced Number of Op Amps, IEEE Journal of Solid-State Circuits, vol. 30, No. 12, Dec. 1995.
Seyfi Bazarjani and Martin Snelgrove, A 40 MHz Fourth-Order Double-Sampled SC Bandpass &Sgr;&Dgr; Modulator, 1997 IEEE International Symposium on Circuits and Systems, Jun. 9-12, 1997, Hong Kong.
Hong-Kui Yang and Ezz I. El-Masry, Double Sampling Delta-Sigma Modulators, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 43, No. 7, Jul. 1996.
Adrian K. Ong and Bruce A Wooley, A Two-Path Bandpass &Sgr;&Dgr; Modulator for Digital if Extraction at 20 MHz, IEEE Journal of Solid State Circuits, vol. 32, No. 12, Dec. 1997.
Armond Hairapetian, An 81-MHz iF Receiver in CMOS, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996.

Affiliated with

Also associated with

Rating

Double-sampling pseudo-3-path bandpass sigma-delta modulator does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Double-sampling pseudo-3-path bandpass sigma-delta modulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double-sampling pseudo-3-path bandpass sigma-delta modulator will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2542684