Double redundant processor

Details Double redundant processor Double redundant processor

1979-04-12

1982-11-09

Shaw, Gareth D.

Boots, shoes, and leggings

371 9, 371 68, G06F 1120

Patent

active

043588239

ABSTRACT:
A double redundant processor including first and second master processors for processing data, control and address signals in a data processing system. The first master processor is in an active state for processing the signals and the second master processor is in a standby state for processing the signals. The first and second master processors include first and second subprocessors for simultaneously processing the data, control and address signals, a comparator connected to compare the signals from the first and second subprocessors, thereby generating a comparison error signal if a disagreement exists, and an alarm monitor responsive to the error signal for inactivating the active master processor and activating the standby master processor.

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Fitzgerald, "Fault-Tolerant Computer Switch", IBM TDM, vol. 20, No. 4, Sep. 1977, pp. 1351-1354.

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