Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2000-02-14
2004-09-28
Kang, Donghee (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S194000, C257S195000, C438S167000, C438S172000, C438S285000
Reexamination Certificate
active
06797994
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to high electron mobility transistors (HEMTs) and more particularly to transistors of such type which are fabricated with a double recess.
As is known in the art, there are several types of active devices used at microwave and millimeter frequencies id to provide amplification of radio frequency signals. In general, one of the more common semiconductor devices used at these frequencies is the high electron mobility transistor (HEMT). Typically, HEMTs are formed from Group III-V materials such as gallium arsenide (GaAs) or indium phosphide (InP). In a HEMT there is a doped donor/undoped spacer layer of one material and an undoped channel layer of a different material. A heterojunction is formed between the doped donor/undoped spacer layer and the undoped channel layer. Due to the conduction band discontinuity at the heterojunction, electrons are injected from the doped donor/undoped spacer layer into the undoped channel layer. Thus, electrons from the large bandgap donor layer are transferred into the narrow bandgap channel layer where they are confined to move only in a plane parallel to the heterojunction. Consequently, there is spatial separation between the donor atoms in the donor layer and the electrons in the channel layer resulting in low impurity scattering and good electron mobility.
One device which has been found to provide good device characteristics such as breakdown voltage, output currents, and pinch-off voltage is a double recessed HEMT. Such a device is fabricated with two aligned recesses in which the gate is formed. The recesses are typically formed by wet etching the device. For example, etching the recesses can include selective and non-selective etching. For non-selective etching, the process is periodically interrupted and the device is tested for certain characteristics, e.g., current. If the characteristics meet the desired criteria, then etching for the recess is terminated. Otherwise, the etching continues. This non-selective process continues until the recess meets the established criteria. This process takes time and money to repeatedly stop the etching and test the device. Also, the etching is not uniform across the wafer, resulting in inconsistent device characteristics across the wafer and low yield of acceptable devices on the wafer.
SUMMARY OF THE INVENTION
In accordance with the present invention, a it transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of Ga
x
In
1−x
As is disposed below and in ohmic contact with the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of Ga
x
In
1−x
As is disposed below the cap layer and provides a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of Al
y
In
1−y
As is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.
With such structure, uniform device characteristics such as breakdown voltage, output currents, and pinch-off voltage are achievable, as is a high yield of acceptable devices.
In accordance with another feature of the invention, a semiconductor structure is provided having a Schottky layer adapted to be etched at a first etch rate by an etchant. The semiconductor structure also has a contact layer disposed above the Schottky layer and adapted to be etched by the etchant at a second etch rate that is substantially faster than the first etch rate. The contact layer provides an opening exposing a region of a top surface of the Schottky layer, the region having a first width. The region of the top surface of the Schottky layer provides a recess of a second width smaller than the first width.
In a preferred embodiment of the invention, the if Schottky layer contains aluminum, with an etch rate of about 0.1 Å/second relative to a succinic acid etchant, while the contact layer is substantially free of aluminum, having an etch rate of about 5 Å/second relative to succinic acid etchant. Such composition allows the transistor's contact layer to be selectively etched with succinic acid to form the opening while leaving the Schottky layer substantially intact. Thus, uniform device characteristics such as breakdown voltage, output currents, and pinch-off voltage can be achieved and a high yield of acceptable devices produced.
In accordance with another feature of the invention, a transistor structure is provided having a Schottky layer adapted to be etched at a first etch rate by an etchant and a contact layer disposed above the Schottky layer and adapted to be etched by the etchant at a second etch rate that is substantially faster than the Schottky layer's first etch rate. In this structure, a region above a portion of a top surface of the Schottky layer is substantially free of the contact layer. The portion of the top surface of the Schottky layer has a first width and provides a recess having a second width smaller than the first width and adapted to receive a gate electrode.
In a preferred embodiment of the invention, the Schottky layer comprises at least about 35 percent Aluminum and the contact layer comprises less than about ten percent Aluminum.
In accordance with another feature of the invention, a double recessed, strain compensated transistor structure is provided. The semiconductor structure has a substrate, a strain compensating layer disposed above the substrate, and a Schottky layer disposed above the strain compensating layer. The substrate and the layers have mismatched lattice constants.
In a preferred embodiment of the invention, the Schottky layer comprises about 60 percent aluminum and about 40 percent indium, and the strain compensating layer comprises about 35 percent gallium and 65 percent indium.
In accordance with another feature of the invention, a method of forming a semiconductor is provided. The method includes forming a Schottky layer adapted to be etched by a first etchant at a first etch rate and forming a contact layer above the Schottky layer adapted to be etched by the first etchant at a second etch rate that is substantially faster than the first etch rate. The first etchant is applied to etch the contact layer to expose a portion of the Schottky layer. A second etchant is applied to etch the portion of the Schottky layer exposed by the first etchant.
In a preferred embodiment of the invention, the Schottky layer contains Aluminum while the contact layer is substantially free of Aluminum. Further, the first etchant includes a carboxylic-acid based wet etchant.
Embodiments of the invention may provide one or more of the following advantages. The invention saves time and money in manufacturing HEMTs. It also decreases the need to etch a device and periodically test the device for certain characteristics. Uniformity of device characteristics on a wafer can be improved.
Other advantages will be apparent from the following description and from the claims.
REFERENCES:
patent: 5060030 (1991-10-01), Hoke
patent: 5140386 (1992-08-01), Huang et al.
patent: 5270228 (1993-12-01), Ishikawa
patent: 5285087 (1994-02-01), Narita et al.
patent: 5298444 (1994-03-01), Ristow
patent: 5300795 (1994-04-01), Saunier et al.
patent: 5364816 (1994-11-01), Boos et al.
patent: 5436470 (1995-07-01), Nakajima
patent: 5448084 (1995-09-01), Hoke et al.
patent: 5504353 (1996-04-01), Kuzuhara
patent: 5548138 (1996-08-01), Tanimoto et al.
patent: 5548140 (1996-08-01), Nguyen et al.
patent: 5550388 (1996-08-01), Haruyama
patent: 5596211 (1997-01-01), Onda et al.
patent: 5641977 (1997-06-01), Kanamori
patent: 5663583 (1997-09-01), Matloubiian et al.
patent: 5668387 (1997-09-01), Streit et
Hoke William E.
Hur Katerina Y.
Daly, Crowley & Mofford, LLP.
Kang Donghee
Raytheon Company
LandOfFree
Double recessed transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Double recessed transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double recessed transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3185184