Double protection virtual ground memory circuit and column...

Details Double protection virtual ground memory circuit and column... Double protection virtual ground memory circuit and column...

2001-05-04

2002-07-16

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S054000

Reexamination Certificate

active

06421296

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90105277, filed on Mar. 7, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a type of virtual ground memory. More particularly, the present invention relates to a double protection virtual ground memory circuit and column decoder.
2. Description of Related Art
In general, the current produced while reading from a virtual ground memory cell is often interfered with by voltage on neighboring bit lines.
FIG. 1
is a schematic circuit diagram of a conventional virtual ground memory. For example, to read data from a memory cell
142
, the bit line
132
is pulled down to a ground voltage while the bit line
134
is pulled up by the voltage biasing circuit
12
. Therefore, the current path starting from the sense amplifier
16
and going through the bit line
134
, the memory cell
142
and the ground-connected bit line
132
is able to sense any data within the memory cell
142
. Although the bit lines
136
and
138
are pulled up to a reference voltage identical to the voltage at the sense amplifier
16
by the voltage biasing circuit
12
when the sense amplifier
16
is in operation so that current is prevented from flowing into the bit lines
136
and
138
, voltage variation on the bit line
130
is likely to affect the potential on the bit line
132
. In other words, the electric potential of the bit line
132
is pulled up when the electric potential on the bit line
130
is greater than zero. In addition, each bit line must couple electrically with a different voltage source (for example, the ground, the sense amplifier
16
, or the voltage biasing circuits
12
and
14
). Hence, a relatively complicated circuit decoder with high consumption of energy has to be designed.
FIG. 2
is a schematic diagram of an alternative conventional virtual ground memory circuit. As shown in
FIG. 2
, voltage biasing of the bit lines (for example, bit lines
260
to
268
) are controlled by the application of a reference voltage VREF to the gate terminals of various transistors (for example, transistors
250
to
258
). To read data from a memory cell
272
, the bit line
262
is grounded while the bit line
264
is coupled to the sense amplifier
20
. Hence, a current path starting from the sense amplifier
20
and going through the bit line
264
, the memory cell
272
and the bit line
262
to ground is established. However, this type of circuit structure has two major drawbacks. First, the bit line
260
is biased, thereby affecting the electric potential of the bit line
262
and reducing current flow. Ultimately, sensing speed and accuracy are compromised. Second, the reference voltage applied to the gates of the various transistors
250
to
258
are difficult to control. When the reference voltage varies, current passing through the transistor
254
also varies, leading to a fluctuation of the detectable range of the sense amplifier
20
.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a double protection virtual ground memory circuit and column decoder. By incorporating a multiple protection circuit, leakage current inside the virtual ground memory is greatly reduced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a type of virtual ground memory having a double protection circuit therein. The virtual ground memory includes at least a memory unit. Data within various memory cells inside the memory unit are sensed by a sense amplifier through a sense terminal. The memory unit includes a plurality of memory cells. A first memory cell having a first conductive terminal, a second conductive terminal and a gate terminal is provided. The first conductive terminal of the first memory cell is electrically coupled to the sense terminal and the second conductive terminal of the first memory cell is connected to ground. The gate terminal of the first memory cell is electrically coupled to a word line. A second memory cell having a first conductive terminal, a second conductive terminal and a gate terminal is provided. The first conductive terminal of the second memory cell is electrically coupled to the output terminal of a voltage biasing circuit. The second conductive terminal of the second memory cell is electrically coupled to the sense terminal and the gate terminal of the second memory cell is electrically coupled to the word line. A third memory cell having a first conductive terminal, a second conductive terminal and a gate terminal is provided. The first conductive terminal of the third memory cell is electrically coupled to the second conductive terminal of the first memory cell and the second conductive terminal of the third memory cell is connected to the ground. The gate terminal of the third memory cell is electrically coupled to the word line. A fourth memory cell having a first conductive terminal, a second conductive terminal and a gate terminal is provided. The first conductive terminal of the fourth memory cell is electrically coupled to the output terminal of the voltage biasing circuit. The second conductive terminal of the fourth memory cell is electrically coupled to the first conductive terminal of the second memory cell and the gate terminal of the fourth memory cell is electrically coupled to the word line.
This invention also provides a double protection virtual ground memory circuit that uses a sense amplifier for sensing memory cell data. The virtual ground memory includes a plurality of bit lines, a voltage biasing circuit, a switching circuit and at least one memory unit. The voltage biasing circuit outputs a bias voltage. The switching circuit has a first output terminal and a second output terminal. The switching circuit receives the bias voltage from the voltage biasing circuit and outputs a signal of different phase from its first output terminal and second output terminal. The memory unit includes a selection circuit and a plurality of pass transistors. The selection circuit receives the signals from the first and second output terminal of the switching circuit and selects the bit lines according to the potential level. A first pass transistor having a first conductive terminal, a second conductive terminal and a gate terminal is provided. The second conductive terminal of the first pass transistor is electrically coupled to a sense amplifier. The gate terminal of the first pass transistor receives a first selection signal. A second pass transistor having a first conductive terminal, a second conductive terminal and a gate terminal is provided. The second conductive terminal of the second pass transistor is electrically coupled to the sense amplifier. The gate terminal of the second pass transistor receives a second selection signal. A third pass transistor having a first conductive terminal, a second conductive terminal and a gate terminal is provided. The second conductive terminal of the third pass transistor is electrically connected to the sense amplifier. The gate terminal of the third pass transistor receives a third selection signal.
This invention also provides a double protection virtual ground memory circuit having a column decoder therein. The virtual ground memory includes a plurality of bit lines, a voltage biasing circuit, a switching circuit and a selection circuit. The voltage biasing circuit outputs a bias voltage. The switching circuit has a first output terminal and a second output terminal. The switching circuit receives the bias voltage and outputs signals each having a different phase from the first output terminal and the second output terminal. The selection circuit receives the signals from the first and second output terminals of the switching circuit for selecting the potential level of the bit lines.
In brief, the double ground-connected protection circuit minimizes the leakage current produced when data within a particular mem

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