Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2000-01-14
2003-05-06
Pan, Daniel H. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S213000, C711S212000, C711S220000, C711S208000
Reexamination Certificate
active
06560694
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of processors and, more particularly, to address and operand sizes in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a processor as described herein. The processor supports an operating mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the operating mode. The operating mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, a first instruction prefix may be coded into an instruction to override the default operand size to a first non-default operand size (e.g. 64 bits). Furthermore, a second instruction prefix may be coded into an instruction in addition to the first instruction prefix to override the default operand size to a second non-default operand size (e.g. 16 bits). Thus, operand sizes of 64, 32, and 16 bits may be used when desired.
Broadly speaking, a processor comprising an execution core is contemplated. The execution core is configured to execute a first instruction having a first instruction prefix and a second instruction prefix, wherein a combination of the first instruction prefix and the second instruction prefix specifies that a default operand size of the processor be overridden with a first operand size. Additionally, a computer system is contemplated including the processor and an input/output (I/O) device configured to communicate between the computer system and another computer system to which the I/O device is couplable.
Moreover, a method is contemplated. A first instruction which includes a first instruction prefix and a second instruction prefix is executed. A combination of the first instruction prefix and the second instruction prefix specifies that a default operand size of a processor be overridden with a first operand size. The default operand size is overridden by the first operand size during execution of the first instruction.
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Keller James B.
McGrath Kevin J.
Advanced Micro Devices , Inc.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Pan Daniel H.
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