Double polysilicon process for fabricating CMOS integrated circu

Details Double polysilicon process for fabricating CMOS integrated circu Double polysilicon process for fabricating CMOS integrated circu

1983-09-29

1985-05-21

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, H01L 21265, H01L 2131

Patent

active

045177317

ABSTRACT:
A process is disclosed for fabricating complementary n and p channel insulated gate field effect transistors. The process uses two layers of polycrystalline silicon 32 and 44 to provide electrical interconnections, and allows the formation of microcapacitors between the two layers of polycrystalline silicon. In addition silicon dioxide and silicon nitride, and two layers of photoresist, are used as masks against heavy boron implantations. The reliability of ohmic connections between aluminum 50 and contact regions in the substrate is enhanced by providing additional dopant to the contact regions. In this way, the junction depth is increased and electrical defects caused by metal spiking are minimized.

REFERENCES:
patent: 4135955 (1979-01-01), Gasner et al.
patent: 4192059 (1980-03-01), Khan et al.
patent: 4391650 (1983-07-01), Pfeifer et al.
patent: 4397077 (1983-08-01), Derbenwick et al.
patent: 4409723 (1983-10-01), Harari
patent: 4420871 (1983-12-01), Scheibe
patent: 4451841 (1984-05-01), Hori et al.

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