Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1986-05-12
1987-07-14
Chaudhuri, Olik
Metal working
Method of mechanical manufacture
Assembling or joining
29576C, H01L 2704, H01L 2978
Patent
active
046793020
ABSTRACT:
In a double polysilicon integrated circuit processing method a first level polysilicon is used for FET gate fabrication, a second level is used for interconnection and both levels are used in the fabrication of analog capacitors over field oxide regions. By the invention, capacitors are also fabricated in the FET device well by implanting dopant through the second level polysilicon at the same time that dopant is implanted directly into other regions of the substrate to a greater depth and dopant level concentration so as to function as an FET source. The method is particularly adapted to fabricating DRAM memories.
REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3996658 (1976-12-01), Takei et al.
patent: 4021789 (1977-05-01), Furman et al.
patent: 4080718 (1978-03-01), Richman
patent: 4261772 (1981-04-01), Lane
patent: 4350536 (1982-09-01), Nakano et al.
patent: 4397077 (1983-08-01), Derbenwick et al.
patent: 4466177 (1984-08-01), Chao
patent: 4577390 (1986-03-01), Haken
Klepner et al., IBM Tech. Disc. Bull., V. 19, No. 2 (Jul. 1976), pp. 458-459.
Rideout, IBM Tech. Disc. Bull., V. 21, No. 9 (Feb. 1979), pp. 3823-3825.
Lu, IBM Tech. Disc. Bull., V. 26, No. 3B (Aug. 1983), pp. 1318-1322.
Hogeboom John G.
Theriault Robert E.
Chaudhuri Olik
Mowle John E.
Northern Telecom Limited
LandOfFree
Double polysilicon integrated circuit process does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Double polysilicon integrated circuit process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double polysilicon integrated circuit process will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1420076