Double polysilicon capacitor formation compatable with submicron

Details Double polysilicon capacitor formation compatable with submicron Double polysilicon capacitor formation compatable with submicron

1991-08-01

1992-12-22

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 52, 437228, 437229, 437919, H01L 2170

Patent

active

051734370

ABSTRACT:
A method for fabricating an integrated circuit having a double polysilicon capacitors and metal oxide silicon field effect devices which are compatible to one micrometer or less processing is described. First, a pattern of recessed oxide isolation is formed on the surface of a silicon substrate. The pattern separates surface regions of silicon from other such regions. A gate dielectric layer is formed on the surface of surface regions of the silicon with a suitable dopant concentration. A first polysilicon layer is formed over the gate dielectric layer and over the field oxide having a suitable doping concentration. An interpoly dielectric layer is formed over the surface of the first polysilicon layer. A second poly silicon layer is formed over the interpoly dielectric layer having a suitable doping concentration. The second polysilicon layer is patterned using a first resist masking and suitable etching to leave only the top plate of the capacitor in the second polysilicon layer. The interpoly dielectric layer is removed except where it is located beneath the top plate by using top plate of the capacitor in second polysilicon layer as the etching mask. The first polysilicon layer is now patterned using a second resist masking and suitable etching to leave only the bottom plate of the capacitor and the gate electrode of the transistor in the first polysilicon layer. The second resist masking layer is removed. The elements of the integrated circuit are completed by conventional processing.

REFERENCES:
patent: 5037772 (1991-08-01), McDonald

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