Double poly trenched channel accelerated tunneling electron (DPT

Details Double poly trenched channel accelerated tunneling electron (DPT Double poly trenched channel accelerated tunneling electron (DPT

1994-05-16

1996-04-09

Nguyen, Viet Q.

Horology: time measuring systems or devices

Regulating means

For setting

257321, 36518528, H01L 2978, G11C 1300

Patent

active

055064310

ABSTRACT:
A structure for low voltage, high density, non-volatile memory cell, with ability to write electrically using the CACT or Channel Accelerated Carrier Tunneling method for programming memories and erase electrically by tunneling, having separate regions for write and erase for high reliability, is described. These cells have the ability to write by transferring charge to the storage gate using the majority carriers in the channel of the MOS transistor, eliminating the need for generation of high fields needed for the hot electron EPROM write method used in the prior art flash memories. In addition the use of the carrier velocity to enhance the write process reduce the need for the high write -voltages on the gates as compared to the present EEPROM and EPROM write memories.

REFERENCES:
patent: Re33261 (1990-07-01), Baglee
patent: 4855800 (1989-08-01), Esquivel et al.
patent: 5146426 (1992-09-01), Mukherjee et al.

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