Double PLL device

Details Double PLL device Double PLL device

1991-11-05

1993-03-16

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 2, 331 17, 331DIG2, 375110, 375120, H03L 7095, H03L 7107, H03L 707, H03D 324

Patent

active

051948281

ABSTRACT:
In a second PLL circuit 200, a phase comparator 13 compares the phase of a clock B' from a frequency divider 11 with the phase of a clock A' from a first PLL circuit 100 to transmit a comparison result to low pass filters X and Y in a filter circuit 14. A phase shift detector 12 detects a phase shift between the clocks A' and B' to output a detection signal E corresponding to the phase shift. A selector 15 selectively outputs an output of either the low pass filter X or Y in response to the detection signal E to input it to a VCXO 10. When the phase shift between the clocks A' and B' exceeds a predetermined value, the low pass filter Y having a high cut-off frequency is selected, whereby the second PLL circuit 200 responds rapidly, and the clock B' follows the clock A' quickly.

REFERENCES:
patent: 4617520 (1986-10-01), Levine

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