Double phase lock loop arrangement

Details Double phase lock loop arrangement Double phase lock loop arrangement

1981-06-22

1983-08-16

Ng, Jin F.

Telecommunications

Receiver or analog modulated signal frequency converter

Local control of receiver operation

455265, 331 2, 331 12, H04B 116, H03L 706

Patent

active

043995608

ABSTRACT:
The double phase lock loop arrangement of the invention comprises a first feedback loop including a first voltage controlled oscillator (16), a second feedback loop including a second voltage controlled oscillator (20) and first (PSD1), second (PSD2) and third (PSD3) phase sensitive detectors. Each of the detectors have first and second inputs and an output, each first input being coupled to receive a signal which is derived from the first voltage controlled oscillator (16). The second voltage controlled oscillator (20) is connected to the second inputs of the first and second phase sensitive detectors (PSD1, PSD2) and via a phase shifter (21) to the second input of the third phase sensitive detector (PSD3) on whose output a lock signal is produced in response to the signals on its first and second inputs being in a desired phase relationship. The output of the second phase sensitive detector (PSD2) is an A.C. correction signal which is applied via a high pass filter (32) to the input of the second voltage controlled oscillator (20). The output of the first phase sensitive detector (PSD1) is a D.C. correction signal which, prior to the lock signal being produced, is applied to the second voltage controlled oscillator (20) to adjust the output frequency thereof and which, after the production of the lock signal, is applied to the first voltage controlled oscillator to adjust the output frequency thereof.

REFERENCES:
patent: 3336534 (1967-08-01), Gluth
patent: 4322751 (1982-03-01), Hongu et al.

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