Double master mask process for integrated circuit manufacture

Details Double master mask process for integrated circuit manufacture Double master mask process for integrated circuit manufacture

1976-06-28

1977-05-03

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, H01L 21265

Patent

active

040212700

ABSTRACT:
A double master mask process for fabricating semiconductor integrated circuits is provided in which selectively etchable dielectric layers and ion implanted resistors are used to form dense integrated circuits with a minimum number of critical alignments. A first silicon dioxide silicon nitride layer used in conjunction with a first master photomask defines a base region and an isolation region which are self-aligned with respect to each other and with respect to resistor contact regions. After isolation and base diffusion, the first oxide
itride layer is stripped away and a second oxide
itride layer is grown. Using a photoresist mask, a predeposition layer for the resistor is then formed using ion implantation through the oxide
itride layers. A second master photomask allows the formation of collector and emitter regions and base and resistor contact which are self-aligned with respect to each other. The diffusion cycle used to form the collector contact and emitter regions simultaneously anneals the ion implanted resistor region to form a high value resistor of closely controlled tolerances. In conjunction with the use of the first master mask, a base region and isolation region which are self-aligned with respect to each other are formed through the use of a " base washout" process which maintains self-alignment without the use of additional process steps.

REFERENCES:
patent: 3673679 (1972-07-01), Carbajal et al.
patent: 3771218 (1973-11-01), Langdon
patent: 3793088 (1974-02-01), Eckton, Jr. et al.
patent: 3865652 (1975-02-01), Agusta et al.

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