Double mask process for forming trenches and contacts during the

Details Double mask process for forming trenches and contacts during the Double mask process for forming trenches and contacts during the

1994-10-06

1995-11-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437235, 148DIG106, H01L 2144, H01L 2148

Patent

active

054666392

ABSTRACT:
A method of forming contact to a semiconductor memory device feature comprises the steps of forming a first oxide layer over a feature such as a semiconductor substrate or a conductive line or plate, then forming a hard mask over the first oxide layer. A first patterned resist layer is formed on the hard mask, then the hard mask is patterned using the first resist layer as a pattern. The first resist layer is removed and a second oxide layer is formed over the hard mask. A second patterned resist layer is formed over the second oxide layer and the second oxide layer is etched using the second resist layer as a pattern while, during a single etch step, the first oxide layer is etched using the hard mask as a pattern, the hard mask functioning as an etch stop. The second resist layer is removed and a conductive layer is formed over the second dielectric layer and the hard mask, with the conductive layer (including any adhesion layers required to adhere the conductive layer to the underlying layer), contacting the feature and forming contacts. The conductive layer is then planarized.

REFERENCES:
patent: 4997789 (1991-03-01), Keller et al.
patent: 5055423 (1991-10-01), Smith et al.
patent: 5354711 (1994-10-01), Heitzmann et al.
patent: 5397908 (1995-03-01), Dennison et al.
patent: 5403781 (1995-04-01), Matsumoto et al.
Ueno et al, "A Quarter-Micron Planarized Interconnection Technology with Self-Aligned Plug", Apr. 1992 IEEE, pp. 305-308.
Kaanta et al., "Dual Damascene: A ULSI Wiring Technology", Jun. 11-12, 1991 IEEE, VMIC Conference, pp. 144-152.

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