Double-gated transistor circuit

Details Double-gated transistor circuit Double-gated transistor circuit

2006-12-26

2006-12-26

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S347000

Reexamination Certificate

active

07154135

ABSTRACT:
An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

REFERENCES:
patent: 6248626 (2001-06-01), Kumar et al.
patent: 6580137 (2003-06-01), Parke
patent: 2002/0093053 (2002-07-01), Chan et al.
patent: 2002/0105039 (2002-08-01), Hanafi et al.
patent: 2004/0041591 (2004-03-01), Forbes
Lee et al., “Super Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy”, IEEE, 1999, pp. 3.5.1-3.5.4.

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