Double-gated semiconductor memory device

Details Double-gated semiconductor memory device Double-gated semiconductor memory device

1990-11-20

1991-10-15

James, Andrew J.

Static information storage and retrieval

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Guide structure

357 42, 357 237, 365154, H01L 2904, H01L 2702, H01L 2701, G11C 1100

Patent

active

050578987

ABSTRACT:
A double-gated MOS type semiconductor memory device having a pair of inverters each of which comprises a bulk MOS transistor formed in a semiconductor substrate and having a first gate electrode on the substrate, and a complementary type MOS transistor stacked over and connected with the bulk MOS transistor, the complementary tyupe MOS transistor being composed of a first insulating film, a semiconductor active layer, a second insulating film and a second gate electrode, laminated upwardly in this order on the first gate electrode, and a process for preparing the double-gated MOS type semiconductor memory device.

REFERENCES:
patent: 4653025 (1987-03-01), Minato et al.
patent: 4656731 (1987-04-01), Lam et al.
patent: 4768076 (1988-08-01), Aoki et al.
patent: 4894801 (1990-01-01), Saito et al.
Chen et al., "Stacked CMOS SCRAM Cell", IEEE Electron Device Letters, vol. EDL-4 (1983) Aug., No. 8, New York, pp. 272-274.
Kawamura et al., "Three-Dimensional CMOS IC's Fabricated by using Beam Recrystallization", IEEE Electron Device Letters, vol. EDL-4, No. 10, Oct. 1983, New York, pp. 366-368.
IEDM 88, CH2528-8/88, 1988, IEEE, pp. 48-51.
Nikkei Microdevices No. 9, 1988, pp. 123-128.
IEEE Electron Device Letters, vol. 9, No. 1, Jan. 1988, pp. 48-51.

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