Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2001-11-19
2002-08-13
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S328000
Reexamination Certificate
active
06433609
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to active clamp circuits for providing electrical overshoot and undershoot protection, particularly in double gate silicon on insulator (SOI) integrated circuit applications.
DESCRIPTION OF RELATED ART
Over the years, digital circuits, and the voltage levels associated therewith, have decreased in size in order to keep up with modern technology. In so doing, modern digital circuits which operate at one voltage level may need to transfer signals to and/or receive signals from circuits operating at other voltage levels. Clamping circuits have been introduced in the art to allow circuits to transfer signals to and/or receive signals from circuits operating at differing voltages by partially terminating and protecting each circuit from voltages that are outside its operating range.
Clamping circuits maintain voltages within an acceptable range by controlling electrical overshoot (positive) and undershoot (negative) at the signal input of a digital circuit to provide a reliable logic signal under adverse and noisy conditions. In an ideal system, the input voltage to each element in a digital circuit will be in only one of two distinct logic states, either an upper digital voltage or a lower digital voltage. The upper digital voltage (or positive terminal) of the power supply (referred to herein as Vdd) corresponds to the digital ones of the circuit and is typically +5 volts and may be 3.3, 2.5, 1.8, 1.2 volts or even lower in newer designs. The lower digital voltage of the power supply (referred to herein as Vss) corresponds to the digital zeros of the circuit and is typically at ground potential which may be zero volts.
Ideally, the input voltage switches instantly between the up state and the down state, never going above the upper voltage nor below the lower voltage, and spending substantially no time at any intervening voltage between the two states. However, in real circuits the input voltage generally takes a finite amount of time to switch between the two logic states wherein the input voltage often exceeds the upper limit, i.e., overshoots the voltage, and oscillates (or rings) around this new voltage before settling down. Clamping circuits have been designed to minimize such ringing as it can seriously degrade the circuit's performance. Typically, a good clamping circuit dampens ringing and reduces noise so that the signal at the input remains at or near one of the two desired voltage states (Vdd or Vss) and switches between these two states quickly and cleanly.
Improved clamping performance comes about by supplying or draining current as quickly as possible to/from the network at the input to the circuit being clamped whenever the voltage at the input exceeds or falls below the two desired voltage states. In order to supply sufficient current, the clamping circuit should have low impedance and a low reflection coefficient in the vicinity of the upper and lower voltages corresponding to the two digital logic states. However, in order to maximize switching speed between the two logic states, the impedance of the clamping circuit and the reflection coefficient should be very high during switching for the brief time when the input voltage is between the upper and lower digital voltages. Currently used passive clamping circuits are unable to effectively meet these opposing requirements for the highest performance applications.
Typically, in a passive clamping circuit, any excess signal voltage on the input is pulled towards or clamped to the positive Vdd supply voltage while any lower signal voltage state is pulled towards or clamped to the lower voltage supply Vss or ground. As transistors continually decrease in size and the upper digital voltage of the power supply (Vdd) associated therewith decreases, i.e., 1.2 volts or even lower in newer designs, passive clamping circuits are unable to effectively supply or drain current whenever the voltage at the input exceeds or falls below the two desired voltage states.
For example, a typical prior art 5.0 volt system has used a passive clamping circuit in which one diode, having a 0.7 turnout voltage, is placed between the input terminal and Vss (zero volts) and another is placed between the input and Vdd (5.0 volts). The diode between the input terminal and Vdd will conduct when the voltage at the input terminal rises sufficiently above the upper digital voltage to turn on the diode. Thus, this diode limits the input voltage to about 0.7 volts above the desired maximum input voltage, or to about 5.7 volts, but permits 0.7 volt ringing around the upper digital voltage. The second diode is positioned between the input terminal and Vss and conducts when the voltage at the input terminal falls one diode drop below the lower digital voltage (usually zero volts). This prevents ringing in excess of about 0.7 volts, but still permits ringing having a magnitude less than the value needed to turn on the passive diode clamp.
Passive clamp circuits of this type work in 5.0 volt systems because the amplitude of the ringing is relatively small compared to the difference between the upper and lower digital voltages. However, in modern systems having lower maximum input voltages and thus smaller differences between the upper and lower digital voltages, passive clamp circuits of this type are not effective. The 0.7 volt degrades into the noise tolerance of the lower voltage system, such as a 3.3 volt system. Moreover, in 2.5, 1.8, 1.2 and even lower volt systems, such ringing is unacceptable as it produces erratic operation in noisy environments. For example in a 1.0 maximum input volt system, the amplitude of the ringing is large compared to the difference between the upper and lower digital voltages as the diode providing 0.7 volts above the maximum input voltage of 1.0 volt would almost double such voltage, i.e., to about 1.7 volts, causing erratic operation. Accordingly, lower voltage designs need even more careful control over the input signal to prevent erratic operation due to ringing or other noise at the input.
Performance is also improved by driving the input terminal voltage to the upper digital voltage via a connection to Vss when the input voltage is too high (above the upper voltage which is usually Vdd) and by driving the input terminal voltage to the lower digital voltage via a connection to Vdd when the input terminal voltage is too low (below the lower digital voltage which is usually Vss). This increases the speed at which the clamping circuit operates as compared to prior art designs which drive excessively low voltages through a connection to the low voltage supply (Vss) and excessively high voltages through a connection to the high voltage supply (Vdd).
Another requirement for digital circuits is some form of electrostatic discharge (ESD) protection. Generally, separate ESD protection circuits are provided at the input of the circuit to limit the voltage that can be imposed on the circuit at the input terminal even when the circuit is unpowered. It would be desirable if the ESD protection could be incorporated into the clamping circuit. The ability to rapidly supply or drain current is important for both clamping and ESD protection. Older designs for clamping circuits that use current limiting resistors do not provide good ESD protection.
As metal oxide semiconductor technology has improved, MOS devices have been constructed with shorter gate lengths, thinner gate oxides and faster response times. As the gate oxide becomes thinner, the device must be powered with a lower voltage power supply to avoid breakdowns and leakage. Lower power supply voltages are also advantageous in reducing power consumption, decreasing heating, and increasing speed through smaller voltage swings. Good ESD protection for lower voltage designs is critical.
To avoid some of the problems with older MOS devices, source terminated drivers have been used in MOS circuits to lower the drive current of the driver into the net. Unfortunately, this increases delay and slows circuit response. Anothe
Chadurjian Mark F.
Cunningham Terry D.
DeLio & Peterson LLC
Reynolds Kelly M.
Tra Quani
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