Double gate JFET with reduced area consumption and...

Details Double gate JFET with reduced area consumption and... Double gate JFET with reduced area consumption and...

2011-07-05

2011-07-05

Sefer, A. (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S270000, C257S272000, C257S274000, C257S280000, C257S281000, C257S282000, C257S283000, C257SE29312, C257SE29317, C257SE29319, C257SE27080, C257SE27081

Reexamination Certificate

active

07973344

ABSTRACT:
Double gate JFET with reduced area consumption and fabrication method therefore. Double-gate semiconductor device including a substrate having a shallow trench isolator region comprising a first STI and a second STI, a channel region having a first and second channel edges, the channel region formed in the substrate and disposed between and in contact with the first STI and the second STI at the first and second channel edge. The first STI has a first cavity at the first channel edge, and the second STI has a second cavity at the second channel edge. The device further includes a gate electrode region comprising conductive material filling at least one of the first and second cavities. At least one of the first and second cavities is physically configured to provide electrical coupling of the gate electrode region to a back-gate P-N junction.

REFERENCES:
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patent: 5972758 (1999-10-01), Liang
patent: 6277697 (2001-08-01), Lee
patent: 7557393 (2009-07-01), Vora
patent: 2004/0058499 (2004-03-01), Ishitsuka et al.
patent: 2005/0173726 (2005-08-01), Potts
Parke S., et al. “Flexfet: A Low-Cost, Rad-Hard, Independent-Double-Gate SOI CMOS Technology with Flexible, Dynamic Reconfigurability” Aerospace, 2005 IEEE Conference Big Sky, MT. USA May 12, 2005, Piscataway. NJ USA, IEEE. Pitcataway, NJ. USA, pp. 1-8.

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