Double edge trigger d-type flip-flop

Details Double edge trigger d-type flip-flop Double edge trigger d-type flip-flop

1999-04-06

2001-05-29

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000

Reexamination Certificate

active

06239640

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a flip-flop, and more particularly, to a double edge trigger D-type flip-flop.
BACKGROUND OF THE INVENTION
A conventional flip-flop is triggered either at the rising edge (or positive level) or the falling edge (negative level) of a clock cycle. The structure of the conventional rising edge trigger D-type flip-flop mainly consists of inverters and tri-state inverters. The basic circuit structure of a tri-state inverter is illustrated in FIG.
1
. The operation of the tri-state inverter is described as follows: when the clock control signal CKP is logical “0” (the inverted clock control signal CKN is now logical “1”), the tri-state inverter is acted as an inverter; on the contrary, when the clock control signal CKP is logical “1” (the inverted clock control signal CKN is now logical “0”), the output Z of the tri-state inverter is floating (i.e., high impedance). Such a circuit is so-called a “tri-state inverter” due to the output thereof having three states, i.e., “0”, “1” and “floating”.
Referring to
FIG. 2
, it illustrates the circuit structure of a conventional rising edge trigger D-type flip-flop. The rising edge trigger D-type flip-flop consists of two tri-state inverters (
20
,
22
), two latches (
21
,
23
), clock control signal (CK) and inverted clock control signal (CKB). Latch (
21
) consists of two inverters (
211
,
212
), wherein the output Z of the inverter (
211
) is connected to the input A of the inverter (
212
) and the output of the inverter (
212
) is connected to the input of the inverter (
211
). Such a connection forms a positive feedback circuit. Therefore, the value of the output N
2
of the latch (
21
) can be maintained even if the input NI of the latch (
21
) is floating. The circuit structure of latch (
23
) is similar to that of latch (
21
).
The operation of the conventional rising edge trigger D-type flip-flop is described as follows: when the clock control signal CK is logical “0” (the inversed clock control signal CKB is now logical “1”), the tri-state inverter (
20
) is acted as an inverter and the other tri-state inverter (
22
) is floating ( i.e., the output N
3
of the tri-state inverter (
22
) has a high impedance), therefore, the input D is inversed by tri-state inverter (
20
) and latched in latch
1
(
21
) but cannot be transmitted to latch
2
(
23
); when the clock control signal CK is changed from logical “0” to logical “1” (the inversed clock control signal CKB is now changed from logical “1” to logical “0”), the tri-state inverter (
22
) is acted as an inverter and the other tri-state inverter (
20
) is floating, therefore, the input D cannot be latched in latch
1
(
21
) and the data previously latched in latch
1
(
21
) is inversed by tri-state inverter (
22
) and latched in latch
2
(
23
) and finally transmitted to output Q of the flip-flop.
Therefore, the conventional rising edge D-type flip-flop is capable of performing one bit access during a clock cycle. However, the operation is merely performed at the rising edge of a clock and cannot be performed at the falling edge of the clock. Therefore, there is a need to overcome such an inefficient operation.
SUMMARY OF THE INVENTION
To overcome the aforementioned problems, it is an object of the present invention to provide a double edge trigger D-type flip-flop which can be both triggered at the rising edge and falling edge of a clock. That is to say, the double edge trigger D-type flip-flop of the present invention can access data twice in a clock cycle. Therefore, the double edge trigger D-type flip-flop of the present invention is capable of providing a double accessed data amount than that of a conventional rising (or falling) edge trigger D-type flip-flop, thereby significantly increasing the efficiency of the system.


REFERENCES:
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 5767716 (1998-06-01), Ko
patent: 5867049 (1999-02-01), Mohd

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