Double DRAM cell

Details Double DRAM cell Double DRAM cell

1991-05-20

1992-06-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 89, 437915, H01L 2170, H01L 2120

Patent

active

051224763

ABSTRACT:
A double dynamic random access memory (DRAM) cell comprising two vertically stacked access transistors and storage capacitors. A first access transistor is formed on a silicon substrate. A seed contact to the first access transistor is then utilized for growing an intermediate silicon substrate by Confined Lateral Selective Epitaxial Overgrowth (CLSEG). A second access transistor is formed upon the intermediate silicon substrate. A storage capacitor for the first access transistor may be formed as a trench capacitor in the silicon substrate. A storage capacitor for the second access transistor may be stacked on the second access transistor. A common buried bit line connects the two access transistors.

REFERENCES:
patent: 4760036 (1988-07-01), Schubert
patent: 4902637 (1990-02-01), Kondou et al.
patent: 4927779 (1990-05-01), Dhong et al.

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