Double diffusion metal-oxide-semiconductor device having shallow

Details Double diffusion metal-oxide-semiconductor device having shallow Double diffusion metal-oxide-semiconductor device having shallow

1990-09-05

1991-09-03

James, Andrew J.

357 42, 357 59, 357 63, H01L 2910, H01L 2978, H01L 2702, H01L 2904

Patent

active

050459015

ABSTRACT:
A MOS transistor comprises source and drain impurity regions on a surface of a silicon substrate. The source and drain regions have a double diffusion structure including impurity regions of high concentration and impurity regions of low concentration surrounding the high-concentration impurity regions. Outgoing electrode layers of polysilicon are formed on surfaces of the source and drain impurity regions. A gate electrode is formed to partially extend over the outgoing electrode layers for the source and drain impurity regions. The source and drain impurity regions are formed by implanting impurities into the electrode layers and subsequently diffusing the impurities into the semiconductor substrate by thermal diffusion. Those processes of impurity implantation and thermal diffusion are effected after completion of the step of patterning the gate electrode. Since thermal diffusion of the impurity implantation for the source and drain regions occurs as a final heat treatment step in the process, the depth of the impurity implanted regions can be precisely controlled.

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